This introduction into the Efinix Trion T120 FPGA Evaluation Kit walks through implementing VexRiscv Ruby SoC RISC-V Soft CPU on Efinix Trion T120. Topics include connecting a JTAG, installing Efinity, building the RISC-V, programming the on-board configuration memory, and running example RISC-V projects.
- T120 Trion® FPGA Evaluation Board at Digi-Key
Efinity® Integrated Development Environment
This project requires Efinity® Integrated Development Environment v2020.1.140
Zadig USB driver installation made easy
Download Zadig, which is a Windows application that installs generic USB driver
- Open the Zadig software.
- Choose Options > List All Devices.
- Turn off Options > Ignore Hubs or Composite Parents.
- Select the Trion T120F324 Development Board (Interface 0)
- Select libusbK (version) next to Driver.
- Click Replace Driver.
- Repeat with the Trion T120F324 Development Board (Interface 1)
Extract efx_ruby_riscv_soc-v1.1zip into C:/riscv/
Extract riscv_sdk_windows-v1.1zip into C:/riscv-sdk/
Programming the Development Board
On the F324 Board, make sure to set J10 to use the 10Mhz Oscillator option.