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  • DAC AD5628 Pmod Controller (VHDL)

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The default value specified in the code is spi_clk_div = 1.  This is arrived at because any clk_freq ≤ 100 MHz results in the default spi_clk_div = 1.  For instance, the component was developed and tested using a system clock of 50 MHz.  50/100 = 0.5, rounded up is 1. 

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Equation 2 defines the serial clock frequency fsclk that results.

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This calculation keeps the serial clock below the DAC’s maximum specified communication frequency of 50 MHz.  The fastest communication occurs when the input clock frequency (in MHz) is an integer multiple of 100.

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