The mclk signal can be derived inside the FPGA using a PLL.
Table 2 1 describes the I2S Transceiver’s ports.
Table 21. Port Descriptions
|reset_n||1||in||standard logic||user logic||Asynchronous active low reset|
|mclk||1||in||standard logic||user logic||Master clock from which sclk and ws are derived|
|sclk||1||out||standard logic||I2S device||Serial clock (i.e. bit clock)|
|ws||1||out||standard logic||I2S device||Word select (i.e. left right clk)|
|sd_tx||1||out||standard logic||I2S device||Serial data transmit|
|sd_rx||1||in||standard logic||I2S device||Serial data receive|
|l_data_tx||N*||in||standard logic vector||user logic||Left channel data word to transmit|
|r_data_tx||N*||in||standard logic vector||user logic||Right channel data word to transmit|
|l_data_rx||N*||out||standard logic vector||user logic||Left channel data word received|
|r_data_rx||N*||out||standard logic vector||user logic||Right channel data word received|
* N is the specified data width, set by the d_width generic
The reset_n input port must have a logic high for the I2S Transceiver to operate. A low signal on this port asynchronously resets the component. During reset, the component holds the sclk, ws, and sd_tx ports low. Any transmit currently underway is discontinued. Any receive currently in progress is abandoned, and the l_data_rx and r_data_rx output ports clear. All internal data buffers are cleared. Once released from reset, the I2S Transceiver resumes operation.