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The mclk signal can be derived inside the FPGA using a PLL.

Port Descriptions

Table 2 1 describes the I2S Transceiver’s ports.

Table 21.  Port Descriptions

PortWidthModeData TypeInterfaceDescription
reset_n1instandard logicuser logicAsynchronous active low reset
mclk1instandard logicuser logicMaster clock from which sclk and ws are derived
sclk1outstandard logicI2S deviceSerial clock (i.e. bit clock)
ws1outstandard logicI2S deviceWord select (i.e. left right clk)
sd_tx1outstandard logicI2S deviceSerial data transmit
sd_rx1instandard logicI2S deviceSerial data receive
l_data_txN*instandard logic vectoruser logicLeft channel data word to transmit
r_data_txN*instandard logic vectoruser logicRight channel data word to transmit
l_data_rxN*outstandard logic vectoruser logicLeft channel data word received
r_data_rxN*outstandard logic vectoruser logicRight channel data word received
* N is the specified data width, set by the d_width generic


The reset_n input port must have a logic high for the I2S Transceiver to operate.  A low signal on this port asynchronously resets the component.  During reset, the component holds the sclk, ws, and sd_tx ports low.  Any transmit currently underway is discontinued.  Any receive currently in progress is abandoned, and the l_data_rx and r_data_rx output ports clear.  All internal data buffers are cleared.  Once released from reset, the I2S Transceiver resumes operation.