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Table 2.  Port Descriptions

PortWidthModeData TypeInterfaceDescription
clk1instandard logicuser logicSystem clock
wr_ena1instandard logicuser logicWrite enable: synchronously writes data on data_in port to the memory location specified on addr port when ‘1’
addrM^inintegeruser logicAddress of memory location to access
data_inN*instandard logic vectoruser logicData to be written to memory location addr if wr_ena is asserted
data_outN*outstandard logic vectoruser logicData currently stored in memory location addr