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Table 2. Port Descriptions
| Port | Width | Mode | Data Type | Interface | Description |
|---|---|---|---|---|---|
| clk | 1 | in | standard logic | user logic | System clock |
| wr_ena | 1 | in | standard logic | user logic | Write enable: synchronously writes data on data_in port to the memory location specified on addr port when ‘1’ |
| addr | M^ | in | integer | user logic | Address of memory location to access |
| data_in | N* | in | standard logic vector | user logic | Data to be written to memory location addr if wr_ena is asserted |
| data_out | N* | out | standard logic vector | user logic | Data currently stored in memory location addr |
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