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  • Serial Peripheral Interface (SPI) Master (VHDL)

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Port

Width

Mode

Data Type

Interface

Description

clock

1

in

standard logic

user logic

System clock.

reset_n

1

in

standard logic

user logic

Asynchronous active low reset.

enable

1

in

standard logic

user logic

H: latches in settings, address, and data to initiate a transaction, L: no transaction is initiated.

cpol

1

in

standard logic

user logic

SPI clock polarity setting.

cpha

1

in

standard logic

user logic

SPI clock phase setting.

cont

1

in

standard logic

user logic

Continuous mode flag.

clk_div

32

in

integer

user logic

Speed setting.  The integer input is the number of system clocks per 1/2 period of sclk.

addr

32

in

integer

user logic

Address of target slave.  The slaves are assigned addresses starting with 0.

tx_data

M*

in

standard logic vector

user logic

Data to transmit.

miso

1

in

standard logic

slave devices

Master in, slave out data line.

sclk

1

buffer

standard logic

slave devices

SPI clock.

ss_n

N^

buffer

standard logic vector

slave devices

Slave select signals.

mosi

1

out

standard logic

slave devices

Master out, slave in data line.

busy

1

out

standard logic

user logic

Busy / data ready signal.

 

 



rx_data

M*

out

standard logic vector

user logic

Data received from target slave.

 

 



Notes
* M is the specified data width, set by the d_width generic
^ N is the specified number of slaves, set by the slaves generic

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Accelerometer ADXL345 Pmod Controller (VHDL) – This design uses the SPI Master component described on this page to communicate with an Analog Devices ADXL345 Accelerometer.  It also demonstrates the use of the Continuous Mode feature of this SPI Master.

Accelerometer ADXL362 Pmod Controller (VHDL) – This design uses the SPI Master component described on this page to communicate with an Analog Devices ADXL362 Accelerometer.  It also demonstrates the use of the Continuous Mode feature of this SPI Master.

Ambient Light Sensor Pmod Controller (VHDL) – This design uses the SPI Master component described on this page to communicate with an ADC.

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