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| Port | Width | Mode | Data Type | Interface | Description |
|---|---|---|---|---|---|
| clk | 1 | in | standard logic | user logic | System clock. |
| reset_n | 1 | in | standard logic | user logic | Asynchronous active low reset. |
| ena | 1 | in | standard logic | user logic | 0: PWM continues outputting current duty cycle. 1: latches in the new duty cycle and adjusts the PWM outputs at the center of their pulses. |
| duty | M* | in | standard _ logic _ vector | user logic | New duty cycle. |
| pwm_out | N^ | out | standard _ logic _ vector | load | Output PWM signals. The PWM modulates around the center of the the pulse. The phases are evenly spaced over the period. |
| pwm_n_out | N^ | out | standard _ logic _ vector | load | Inverse of the PWM outputs. |
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