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Wiki Markup{wiki} {toc:style=disc|indent=20px} h1. Least Mean Square (LMS) Adaptive Line Enhancer (ALE) Design in VHDL h2. Features The Adaptive Line Enhancer (ALE) is an effective learning filter for reducing Gaussian noise with a large SNR. The filter adjusts the filter weights to pass the desired input signal while reducing the noise portion of the signal with little to no filter roll-off up to the Nyquist rate  

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Least Mean Square (LMS) Adaptive Line Enhancer (ALE) Design in VHDL

Features

The Adaptive Line Enhancer (ALE) is an effective learning filter for reducing Gaussian noise with a large SNR. The filter adjusts the filter weights to pass the desired input signal while reducing the noise portion of the signal with little to no filter roll-off up to the Nyquist rate (Fs/2). An adaptive filter can alter its own frequency response in order to improve the filter's filter’s performance on-the-fly. The following design topics will be covered:

ALE filter architecture design fundamentals
Filter stability dependant on learning coefficient, mu
Filter scaling for more efficient implementation
Custom VHDL component design and instantiation to include an 18-bit CODEC controller and ALE filter
Filter characteristics and validation h2. Introduction This reference design utilizes a Xilinx Spartan 6 development board and a National (by Texas Instruments) [LM4550 ac97 audio codec|http://www.digikey.com/product-search/en/integrated-circuits-ics/interface-codecs/2556343?k=lm%204550]. The design was developed in Xilinx ISE ver13.1. This design employs an audio CODEC, but it is not required. The Xilinx Spartan 6 FPGA is a good choice for DSP logic circuit design due to the integrated DSP48A1 blocks. The integrated DSP blocks allow for parallel math circuits resulting in a filter capable of ultra fast data processing. The ALE can be used with any FPGA given enough hardware multipliers, taking into account the word length of the filter. This filter implementation used 48 of the 58 Spartan 6 xc6slx45 DSP48A1 blocks; an FPGA with more DSP blocks can support more ALE taps yielding greater performance. h2. Background It is not necessary that the user of this module have complete understanding of ALE filter design, but it can help in trouble shooting a filter if one understands the basic design principles. This background section covers the fundamentals of the ALE filter and VHDL module design itself. The design uses an internal Gaussian noise generator where the left channel routes the signal before the filter and after the noise, the right channel is the path after the filter where much of the noise is reduced. The effects of the filter on the "noise + signal" and "reduced noise + signal" can be seen in Figures 1 and 2 below. . . . !Fig1_ALE1.jpg|width = 450PX,width=450PX! *Figure 1 -- "Noise + Signal" (Blue) and "Reduced Noise + Signal" (Yellow)* . . . !Fig2_ALE2.jpg|width = 450PX,width=450PX! *Figure 2 -- "Increased Noise + Signal" (Blue) and "Reduced Noise + Signal" (Yellow)* . . . The ALE was also tested with an external noise source from an arbitrary waveform generator. This can be seen in Figure 3 below. . . . !Fig3_ALE3.jpg|width = 450PX,width=450PX! *Figure 3 -- "External Noise + Signal" (yellow) and "Reduced Noise + Signal" (blue)* . . . The adaptive filter excel in filtering signals where one might experience changing conditions, spectral overlap between wide-band noise and the narrow-band signal, or in applications where the noise source is unknown or contentiously changing. The filter changes the weights to reduce noise and maximize the correlated signal output. The ALE's frequency response was plotted in Figure 4 below. Notice how there is not any significant roll-off all the way up through the Nyquist frequency at 24 KHz. . . . !Fig4_Freq_Response.JPG|width = 550PX,width=550PX! *Figure 4 -- ALE Frequency Response up to Nyquist* . . . The input signal ( B(k) + N(k) ) is delayed one sample to de-correlate the Broadband noise signal from itself giving us ( Bu(k) + Nc(k) ). This happens because the noise is random and a small change in phase de-correlates the signal. Notice that the narrow band signal Nc(k) stays correlated with N(k) because it is not random but largely periodic and contentious. The signal flow diagram can be seen in Figure 5 below. . . . !Fig_5_ALE_Sig_Flow.JPG|width = 650PX,width=650PX! *Figure 5 -- ALE Signal Flow Diagram* . . . The ALE filter works by initializing the filter weights to arbitrary values and adjusting them each sample period. This is done by computing the filter output N-hat-k, using equation 1 below. This narrow band signal (N-hat-k) is used to compute the error estimate (ek), see equation 2 below. The ALE implements a least-squares-error cost function to find optimal filter weights to estimate the signal output. Instead of using the expected values from the gradient vector in the parabolic mean-square-error cost function, the current input FIFO values (the instantaneous gradient) are multiplied by a learning coefficient (mu). This adjusts the weights by using a least-mean-square approximation; a step in the greatest decent is taken using equation 3 below. The decent moves down a parabolic structure in n-dimensions, the dimension is determined by the order of the filter. When the gradient is zero the least-mean-squared error has been maximally reduced. To avoid overstepping, we take small steps determined by the learning coefficient mu. The mu value is chosen by using equation 4 below. This mu value governs how much the filter values change in a given sample period. It is handy to choose a value for mu which allows one to simply barrel shift the product of the error estimate and FIFO values, but also important to keep mu small enough to avoid divergence from the error surface of the n-dimensional parabola. A simplified representation of the Mean-Squared-Error surface with two weights can be seen below in Figure 6. . . . !eq1_filter_out_eq.JPG|width = 200PX,width=200PX! validation

Introduction

This reference design utilizes a Xilinx Spartan 6 development board and a National (by Texas Instruments) LM4550 ac97 audio codec. The design was developed in Xilinx ISE ver13.1. This design employs an audio CODEC, but it is not required. The Xilinx Spartan 6 FPGA is a good choice for DSP logic circuit design due to the integrated DSP48A1 blocks. The integrated DSP blocks allow for parallel math circuits resulting in a filter capable of ultra fast data processing. The ALE can be used with any FPGA given enough hardware multipliers, taking into account the word length of the filter. This filter implementation used 48 of the 58 Spartan 6 xc6slx45 DSP48A1 blocks; an FPGA with more DSP blocks can support more ALE taps yielding greater performance.

Background

It is not necessary that the user of this module have complete understanding of ALE filter design, but it can help in trouble shooting a filter if one understands the basic design principles. This background section covers the fundamentals of the ALE filter and VHDL module design itself. The design uses an internal Gaussian noise generator where the left channel routes the signal before the filter and after the noise, the right channel is the path after the filter where much of the noise is reduced. The effects of the filter on the “noise + signal” and “reduced noise + signal” can be seen in Figures 1 and 2 below.
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Image Added
Figure 1 – “Noise + Signal” (Blue) and “Reduced Noise + Signal” (Yellow)
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Image Added
Figure 2 – “Increased Noise + Signal” (Blue) and “Reduced Noise + Signal” (Yellow)
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The ALE was also tested with an external noise source from an arbitrary waveform generator. This can be seen in Figure 3 below.
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Image Added
Figure 3 – “External Noise + Signal” (yellow) and “Reduced Noise + Signal” (blue)
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The adaptive filter excel in filtering signals where one might experience changing conditions, spectral overlap between wide-band noise and the narrow-band signal, or in applications where the noise source is unknown or contentiously changing. The filter changes the weights to reduce noise and maximize the correlated signal output. The ALE’s frequency response was plotted in Figure 4 below. Notice how there is not any significant roll-off all the way up through the Nyquist frequency at 24 KHz.
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Image Added
Figure 4 – ALE Frequency Response up to Nyquist
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The input signal ( B(k) + N(k) ) is delayed one sample to de-correlate the Broadband noise signal from itself giving us ( Bu(k) + Nc(k) ). This happens because the noise is random and a small change in phase de-correlates the signal. Notice that the narrow band signal Nc(k) stays correlated with N(k) because it is not random but largely periodic and contentious. The signal flow diagram can be seen in Figure 5 below.
.
.
.
Image Added
Figure 5 – ALE Signal Flow Diagram
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.
.

The ALE filter works by initializing the filter weights to arbitrary values and adjusting them each sample period. This is done by computing the filter output N-hat-k, using equation 1 below. This narrow band signal (N-hat-k) is used to compute the error estimate (ek), see equation 2 below. The ALE implements a least-squares-error cost function to find optimal filter weights to estimate the signal output. Instead of using the expected values from the gradient vector in the parabolic mean-square-error cost function, the current input FIFO values (the instantaneous gradient) are multiplied by a learning coefficient (mu). This adjusts the weights by using a least-mean-square approximation; a step in the greatest decent is taken using equation 3 below. The decent moves down a parabolic structure in n-dimensions, the dimension is determined by the order of the filter. When the gradient is zero the least-mean-squared error has been maximally reduced. To avoid overstepping, we take small steps determined by the learning coefficient mu. The mu value is chosen by using equation 4 below. This mu value governs how much the filter values change in a given sample period. It is handy to choose a value for mu which allows one to simply barrel shift the product of the error estimate and FIFO values, but also important to keep mu small enough to avoid divergence from the error surface of the n-dimensional parabola. A simplified representation of the Mean-Squared-Error surface with two weights can be seen below in Figure 6.
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.
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Image Added .....................................................Equation 1. !eq2_error_est.JPG|width = 150PX,width=150PX! .

Image Added ..................................................................Equation 2. !eq3_weight_update_eq.JPG|width = 250PX,width=250PX!

Image Added ...........................................Equation 3. !eq4_mu_value.JPG|width = 250PX,width=250PX! 3.

Image Added ..........................................Equation 4.
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. . !Fig6_error_surface.JPG|width = 700PX,width=700PX! *Figure 6 - Simplified Representation of
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Image Added
Figure 6 – Simplified Representation of Mean-Squared-Error Surface*
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. . h2. Application h3. Building the Circuit The ALE filter module uses the following processes: • 16 deep by 18 bit shift register for shifting in samples • State update for timing and flag control • 16 bit linear feedback shift register for dithering during truncation • Timer dependent process for control of data path flags • 16 term parallel multiplier process • Process for truncation and dithering of output terms • Large adder tree as part of convolution • Feedback subtraction process • Error estimation block • Feedback truncation and dithering process • Filter tap adjustment process • 32-bit to 18-bit truncation block for output to DAC . . The ALE architecture can be seen in Figure 7 below. . . . !Fig7_ALEverII.JPG|width = 1050PX,width=1050PX! *Figure 7 -- Adaptive Line Enhancer Filter Architecture* . . . h3. Instantiating the ALE Filter Module The ALE filter is easily instantiated by including the ALE.vhd file in a project and either port mapping the top level ports in Xilinx ISE or using a schematic file to connect to the ports. After creating a schematic symbol within the processes tab, the ports can be connected by adding wires within the schematic editor. The top level schematic can be seen in Figure 8 below. When verifying the module in hardware, the noise_gen.vhd module must be manually reset on the board to seed the pseudo-random number generator. . . . !Fig_8_Top_Lev_Schem.JPG|width = 900PX,width=900PX! *Figure 8 -- Xilinx ISE Schematic Top Level* . . . This application was run at 100MHz with plenty of slack for running at faster speeds . . . h3. Hardware Test and Verification The module was thoroughly tested through the use of Xilinx's simulation software, ISim. A basic timer-driven state machine controls enable flags for synchronizing the math operations, truncating and dithering intermediate operations, and latching in the output each sample period. Each sample period advances the delay lines and starts the flag state machine. The module was also verified in hardware as seen above in Figures 1 through 3. . . . h2. Design Software This reference design utilizes a Xilinx Spartan 6 development board and a National (by Texas Instruments) [LM4550 ac97 audio codec|http://www.digikey.com/product-search/en/integrated-circuits-ics/interface-codecs/2556343?k=lm%204550]. The design was developed in [Xilinx ISE ver13.1|http://www.digikey.com/scripts/dksearch/dksus.dll?FV=fff40028%2Cfff80097&k=xilinx&vendor=0&mnonly=0&newproducts=0&ptm=0&fid=0&quantity=0&PV-5=30339]. The Audio CODEC in this design is not required. The design can be scaled to many non-audio applications, not limited to a 48 KHz sampling rate. . . . h2. Conclusion The adaptive filter excels in filtering signals where one might experience changing conditions, spectral overlap between wide-band noise and the narrow-band signal, or in applications where the noise source is unknown or contentiously changing. This design was targeted and tested in audio applications, although the design can be scaled down for a faster filter with less resolution. The fundamentals of ALE VHDL module's filter design have also been covered. . . . h2. Additional Information The AC97 Codec driver, NbitSatAdder, and noise_gen modules are covered in further detail on the eeWiki Logic page. Further DSP topics and filter design information can be found in the book: Digital Signal Processing, A Practical Approach, By Emmanuel C. Ifeachor and Barrie W. Jervis. For questions relating to this reference design, the author can be contacted at: By Phone: 1-800-338-410 x2969 By Email: !eewikiemailsigwgray.bmp|width = 850PX,width=850PX! h2. Appendix The complete Lattice Diamond project can be downloaded from the Digi-Key, eewiki.net website under the Programmable Logic section. The VHD files are located below. [Least Mean Square (LMS) Adaptive Line Enhancer (ALE) Design in VHDL^ALE.vhd] [Least Mean Square (LMS) Adaptive Line Enhancer (ALE) Design in VHDL^noise_gen.vhd] [Least Mean Square (LMS) Adaptive Line Enhancer (ALE) Design in VHDL^NbitSatAdder.vhd] [Least Mean Square (LMS) Adaptive Line Enhancer (ALE) Design in VHDL^ac97.vhd] [Least Mean Square (LMS) Adaptive Line Enhancer (ALE) Design in VHDL^ac97cmd.vhd] h2. Feedback for Our Sponsor Please take a few seconds to help us justify the continued development and expansion of the eewiki. Click on one of our [Digi-Key|http://www.digikey.com] links on your way to search for or purchase electronic components. Is the eewiki helpful?  Comments, feedback, and questions can be sent to [mailto:eewiki@digikey.com]. {wiki}
.

Application

Building the Circuit

The ALE filter module uses the following processes:
• 16 deep by 18 bit shift register for shifting in samples
• State update for timing and flag control
• 16 bit linear feedback shift register for dithering during truncation
• Timer dependent process for control of data path flags
• 16 term parallel multiplier process
• Process for truncation and dithering of output terms
• Large adder tree as part of convolution
• Feedback subtraction process
• Error estimation block
• Feedback truncation and dithering process
• Filter tap adjustment process
• 32-bit to 18-bit truncation block for output to DAC
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The ALE architecture can be seen in Figure 7 below.
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Image Added
Figure 7 – Adaptive Line Enhancer Filter Architecture
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Instantiating the ALE Filter Module

The ALE filter is easily instantiated by including the ALE.vhd file in a project and either port mapping the top level ports in Xilinx ISE or using a schematic file to connect to the ports. After creating a schematic symbol within the processes tab, the ports can be connected by adding wires within the schematic editor. The top level schematic can be seen in Figure 8 below. When verifying the module in hardware, the noise_gen.vhd module must be manually reset on the board to seed the pseudo-random number generator.
.
.
.

Image Added
Figure 8 – Xilinx ISE Schematic Top Level
.
.
.

This application was run at 100MHz with plenty of slack for running at faster speeds
.
.
.

Hardware Test and Verification

The module was thoroughly tested through the use of Xilinx’s simulation software, ISim. A basic timer-driven state machine controls enable flags for synchronizing the math operations, truncating and dithering intermediate operations, and latching in the output each sample period. Each sample period advances the delay lines and starts the flag state machine. The module was also verified in hardware as seen above in Figures 1 through 3.
.
.
.

Design Software

This reference design utilizes a Xilinx Spartan 6 development board and a National (by Texas Instruments) LM4550 ac97 audio codec. The design was developed in Xilinx ISE ver13.1. The Audio CODEC in this design is not required. The design can be scaled to many non-audio applications, not limited to a 48 KHz sampling rate.
.
.
.

Conclusion

The adaptive filter excels in filtering signals where one might experience changing conditions, spectral overlap between wide-band noise and the narrow-band signal, or in applications where the noise source is unknown or contentiously changing. This design was targeted and tested in audio applications, although the design can be scaled down for a faster filter with less resolution. The fundamentals of ALE VHDL module’s filter design have also been covered.
.
.
.

Additional Information

The AC97 Codec driver, NbitSatAdder, and noise_gen modules are covered in further detail on the eeWiki Logic page. Further DSP topics and filter design information can be found in the book: Digital Signal Processing, A Practical Approach, By Emmanuel C. Ifeachor and Barrie W. Jervis.

For questions relating to this reference design, the author can be contacted at:

 

Appendix

The complete Lattice Diamond project can be downloaded from the Digi-Key, eewiki.net website under the Programmable Logic section. The VHD files are located below.

ALE.vhd
noise_gen.vhd
NbitSatAdder.vhd
ac97.vhd
ac97cmd.vhd

Feedback for Our Sponsor

Please take a few seconds to help us justify the continued development and expansion of the eewiki.

Click on one of our Digi-Key links on your way to search for or purchase electronic components.

Is the eewiki helpful?  Comments, feedback, and questions can be sent to eewiki@digikey.com.