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For simplicity, the reset functionality is not shown in the state diagram.  If at any time the reset_n port is pulled low, the bridge re-initializes and the state machine returns to the ready state.

Port Descriptions

Table 3 1 describes the SPI to I2C bridge’s ports. 

Table 31.  Port Descriptions

Port

Width

Mode

Data Type

Interface

Description

clock

1

in

standard logic

user logic

System clock.

reset_n

1

in

standard logic

user logic

Asynchronous active low reset.

sclk

1

in

standard logic

SPI master device

SPI serial clock.

ss_n

1

in

standard logic

SPI master device

SPI slave select signal.

mosi

1

in

standard logic

SPI master device

SPI master out, slave in data line.

miso

1

out

standard logic

SPI master device

SPI master in, slave out data line.

trdy

1

out

standard logic

SPI master device

The SPI slave's Transmit Ready status register.
0: The SPI master has already accessed the latest result of any I2C transactions.
1: The SPI to I2C bridge has completed a transaction over the I2C port and stored the result in its SPI slave's transmit register.  The result has not yet been accessed by the SPI master.

scl

1

inout

standard logic

I2C slave device

I2C serial clock line.

sda

1

inout

standard logic

I2C slave device

I2C serial data line.

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This bridge implementation enables an SPI master to write and/or read 8-bit I2C slave registers.  Each transaction between the bridge’s SPI slave component and an SPI master must consist of an 8-bit command, followed by a 25-bit data transfer.  Therefore, to execute a transaction, the SPI master sends a 33-bit command to the slave, outlined in Table 12.  The command includes the 8-bit SPI slave command, an I2C enable bit, the 7-bit address of the I2C slave, a read/write bit, an 8-bit register address to access within the I2C slave, and the 8-bit data to write to the I2C slave.  The command is transmitted MSB first.  The SPI slave’s MISO line remains high impedance during the 8-bit SPI slave command, and then returns data during the remaining 25 bits.  See the documentation on the SPI slave for complete timing details here.

Table 12.  Command Format

Table 1 2 also lists the commands necessary to perform various actions.  The first bit of the SPI slave command specifies which register inside the bridge’s SPI slave to write.  ‘0’ indicates the SPI slave’s receive register, where the bridge receives the command and evaluates what to do.  If the I2C enable bit is a ‘1’, the bridge conducts an I2C transaction.  If ‘0’, the bridge ignores the rest of the bits and does nothing on the bus.  This option allows the SPI master to read an I2C result or the bridge’s status register without issuing a new I2C transaction.

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Following each I2C transaction, the bridge loads a 25 bit result into the SPI slave’s transmit register, where it is available to the SPI master, as described above.  Table 2 3 shows the I2C result’s format.  The I2C acknowledge error bit indicates if any I2C slave acknowledge errors occurred during the transaction.  (‘1’ indicates at least one error occurred, ‘0’ indicates no errors.)  The bridge does not retry a transaction in the event of an acknowledge error, so the SPI master must reissue the command if it desires to retry the communication.  The 7-bit I2C slave address, read/write bit, and 8-bit I2C slave register indicate what command had been sent.  The 8 data bits return the data read if the command was a read, and they return the data written if the command was a write.

Table 23.  I2C Result Format

Clock Stretching

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