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  • DAC DAC121S101 Pmod Controller (VHDL)

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Figure 4.  Transaction Example

Port Descriptions

Table 3 1 describes the DAC Pmod Controller’s ports.

Table 31.  Port Descriptions

Port

Width

Mode

Data Type

Interface

Description

clock

1

in

standard logic

user logic

System clock

reset_n

1

in

standard logic

user logic

Asynchronous active low reset

dac_tx_en

1

in

standard logic

user logic

Transaction enable.  H: latches in data for both DACs, then performs a simultaneous transaction with the DACs.  L: no transaction is initiated.

dac_data_a

12

in

standard logic vector

user logic

Data to transmit to DAC A

dac_data_b

12

in

standard logic vector

user logic

Data to transmit to DAC B

busy

1

out

standard logic

user logic

H: component is unavailable.  L: component is ready to accept a new transaction.

mosi_a

1

out

standard logic

DAC Pmod

Serial data output to DAC A

mosi_b

1

out

standard logic

DAC Pmod

Serial data output to DAC B

sclk

1

buffer

standard logic

DAC Pmod

Serial clock

ss_n

1

buffer

standard logic vector

DAC Pmod

Chip select

Connections

This Pmod has a 6-pin connector, J1.  Table 4 2 provides the pinout for this connector.  The DAC Pmod Controller’s ports need to be assigned to the FPGA pins that are routed to this connector as listed.

Table 42.  DAC Pmod Pinout and Connections to DAC Pmod Controller

Pmod Connector

Pmod Pin Number

DAC Pmod Port

DAC Pmod Controller Port

J1

1

~SYNC

ss_n

J1

2

DIN A

mosi_a

J1

3

DIN B

mosi_b

J1

4

SCLK

sclk

J1

5

GND

-

J1

6

VCC

-

Reset

The reset_n input port must have a logic high for the DAC Pmod Controller component to operate.  A low logic level on this port asynchronously resets the component.  During reset, the component aborts the current transaction with the DAC Pmod and sets the busy output high to indicate it is not available.  Once released from reset, the DAC Pmod Controller restarts operation.

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