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  • DAC DAC121S101 Pmod Controller (VHDL)

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This details a VHDL component that handles interfacing to the Digilent’s Pmod DA2 for DAC121S101, shown in Figure 1.  Figure 2 illustrates a typical example of this DAC Pmod Controller integrated into a system.  As shown, the DAC Pmod Controller connects to the Pmod ports and executes transactions to set the DAC outputs.  Data is latched in on simple parallel interfaces which can be connected to user logic or to input ports on the FPGA.

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The design uses the state machine depicted in Figure 3 to implement its operation.  Upon start-up the component immediately enters the start state.  It remains in this state for 100us to ensure the Pmod has ample time to power-up.  It   It then proceeds to the pause state.  Here, it ensures at least 20ns elapse between transactions with DACthe DACs.  At this that point, it deasserts the busy signal to indicate that the DAC Pmod Controller is ready for a new transaction with the DAC Pmod and proceeds to the ready state.  It waits in the ready state until the dac_tx_ena enable signal is asserted, when it latches in the data for the new transaction and advances to the send_data state.  In this state, it executes the transaction with the Pmod and then returns to the pause state.  Although not shown, resetting the component at any time returns it to the start state.

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This calculation keeps the serial clock below the DAC’s maximum specified communication frequency of 30 MHz.  The fastest communication occurs when the input clock frequency (in MHz) is an integer multiple of 60.

Transactions

Example Transaction

The DAC Pmod Controller indicates its availability on its busy output.  When the busy signal is ‘0’, the Controller is ready to accept transactions to send to the DAC Pmod.  Asserting the dac_tx_ena input latches in the current values on dac_data_a and dac_data_b.  Once latched, the Controller asserts the busy signal to indicate that a transaction is in progress, so it is not currently available.  When the transaction is complete, it again deasserts the busy signal to indicate that it’s ready to accept another request.

Example Transaction

Figure 4 illustrates an example transaction.  The busy signal is ‘0’.  The user logic then presents the data “100110011001” to write to DAC A and “010110110011” to write to DAC B.  The Controller asserts the busy signal, indicating the request is latched in, at which point the user logic can deassert the dac_tx_ena signal.  The Controller sends the serial communication to the DAC Pmod, then deasserts busy when complete.  Later, the user logic initiates a new transaction to write “010110010001” to DAC A and “101100111110” to DAC B.

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