Child pages
  • RAM (VHDL)

Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

The RAM is configured by setting the GENERIC parameters in the ENTITY.  Table 2 1 describes the parameters.

Table 21.  Generic Descriptions

GenericData TypeDefaultDescription
d_widthinteger8The width of each data word
sizeinteger64

The number of data words the memory can store

Port Descriptions

Table 1 2 describes the RAM’s ports.

Table 12.  Port Descriptions

PortWidthModeData TypeInterfaceDescription
clk1instandard logicuser logicSystem clock
wr_ena1instandard logicuser logicWrite enable: synchronously writes data on data_in port to the memory location specified on addr port when ‘1’
addrM^inintegeruser logicAddress of memory location to access
data_inN*instandard logic vectoruser logicData to be written to memory location addr if wr_ena is asserted
data_outN*outstandard logic vectoruser logicData currently stored in memory location addr

...