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While most of the discussion surrounding Cypress's PSOC microcontrollers focuses on the digital peripherals and universal digital blocks, the PSOC line of microcontrollers also boast an extensive set of analog peripherals. The purpose of this article is to introduce the user to several of the analog peripherals on the PSOC 5LP as well as provide examples on how to use them. 

This article focuses on the CY8C58LP family. The other variants of the PSOC 5LP, ( the CY8C52LP, CY8C54LP,  and CY8C56LP) contain fewer and/or less capable analog peripherals. However, these peripherals function in the same manner as those described in this article.  

This article assumes the user is familiar with PSOC Creator. 


Cypress CY8CKIT-059: 

The examples shown in this article were developed for Cypress's PSOC 5LP development board, the CY8CKIT-059. This board consists of two sections. The first section consists of Cypress's kitprog programmer/debugger, usb connector, reset button, status led and power status LED. The second section consists of a PSOC 5LP, micro USB connector, user pushbutton, user LED, and breadboard compatible pinouts for the PSOC's GPIO pins.

Further information can be found in the kit's guide which can be downloaded here:  CY8CKIT-059_PSoC5LP_Prototyping_Kit_Guide


 CY8CKIT-059 Pinout



Some other products that may be helpful in performing the examples: 

PRPC022SFAN-RC - 22 pin male breadboarding header 

TW-E40-1020 - solderless breadboard 

Analog to Digital Converter: 

One of the most common peripherals on a microcontroller is the ADC. The PSOC 5LP contains two different types of ADC's, the Successive Approximation (SAR) ADC and the Delta Sigma ADC. 


One can think of the SAR as a general purpose ADC that provides a good compromise between resolution and sampling rate. The PSOC 5LP contains two SAR ADCs which can be configured for 8,10, or 12 bit resolution. The maximum sampling rate of these ADC's is either 500 Ksps without an external bypass capacitor or 1 Msps with an external bypass capacitor. If used, the bypass capacitor should be placed between GPIO pin P0[4] and ground for SAR0 and P0[2] and ground for SAR1. 

The SAR ADC is capable of running in three different modes: 

  • Free Running:
    In this mode the ADC will run continuously. The user can start and stop the conversions by calling the ADC_StartConvert() and ADC_StopConvert() functions in software. 

  • Hardware Trigger:
    With this mode selected, the SAR ADC component will have a SOC (start of conversion) pin. A rising edge pulse on this pin will trigger the start of a single conversion. This mode is best used when the ADC needs to be synchronized with other hardware. 
                                                                                                                                                                                 SAR ADC in hardware trigger mode being driven by a system clock. 

  • Software Trigger: 
    In this mode, a pulse on the SOC pin will trigger conversions in the same manner as the Hardware Trigger mode. However if the user calls the ADC_StartConvert() function, the SOC pin will be disabled and the ADC will start a single conversion. 
    Calling the ADC_StopConvert() function will re-enable the SOC pin and conversions can again be triggered by hardware. So in short, the software trigger mode is basically the same as the hardware trigger mode, except it also lets the user start and stop conversions in software. 



 Using a SAR ADC to interface with an analog distance sensor

The purpose of this example it to demonstrate how to use the SAR ADC to read in data from an analog distance sensor.


  • PSOC 5LP prototyping kit (CY8CKIT-059)
  • Windows PC with PSOC Creator 3.X installed
  • An analog IR distance sensor such as the Sharp Microelectronics GP2Y0A41SK0F
  • IR sensor to servo cable like the one shown here. (makes it much easier to connect the IR sensor to the PSOC)


  1. Download and unzip the example project: SAR Example
  2. Open the project. On the left have of screen, in the workplace explorer window, double click on the "SAR Example.cycdwr" file
  3. This will open the pin selection screen. Ensure that the RX_1 and TX_1 pins are routed to pins 12[6] and 12[7] respectively. Sensor_Pin can be routed to any other GPIO pin.
  4. Connect the distance sensor's power and ground lines to the VDD and Ground pins on the prototyping kit. Connect the sensor's output line to whichever GPIO that Sensor_pin is routed to.
  5. Connect the PSOC 5LP prototyping kit to the pc via USB.
  6. Build the PSOC by selecting the "Build" menu and clicking on the "Build Example" option or alternatively by pressing (shift +F6).
  7. Verify the project builds without errors. Then program the PSOC by selecting the "Debug" menu and clicking on the "Program" option or by pressing ( ctrl + F5).
  8. Use a terminal program to open up a serial connection with the PSOC. Terminal settings should be: baud rate: 115200, data bits: 8, parity :none, stop bits: 1 and flow control: none.
  9. Once the terminal connection is open, press the reset button on the prototyping kit. The output voltage should now be displayed in the terminal window.

Delta Sigma ADC: 

The Delta Sigma ADC is well suited for applications that need high resolution but require a fairly low sampling rate. The PSOC 5LP contains a single Delta Sigma ADC which has a maximum resolution of 20 bits at a sampling rate of 187 sps and a maximum sampling rate of 384 Ksps at 8 bits resolution.

A Delta Sigma ADC consists of two parts; the modulator which over-samples the analog signal and converts it to a bit stream and the digital filter, also called the decimator, which averages the bit stream and sends the resulting samples to the rest of the PSOC. This over-sampling and filtering process increases the ADC's resolution, but has the downside of requiring that several conversions (3 for the PSOC 5LP) are needed to "prime" the ADC before valid results are produced. Luckily for the user, PSOC Creator obfuscates this process and when the ADC is called to make a conversion, it will automatically prime itself before making data available to the rest of the PSOC.  

Like the SAR ADC, the Delta Sigma ADC can either be triggered in software or by a rising pulse on the SOC pin. To enable the SOC pin, the user needs to select "Hardware SOC" under the "common" tab in the Delta Sigma ADC configuration window. 

The Delta Sigma ADC can run in four different sampling modes:

  • Single Sample 
    In this mode, the ADC is in the standby state until it is triggered. Once the  ADC is triggered, it will generate a single valid result. 

  • Continuous
    In this mode, the ADC will continuously perform conversions. These conversions are available to the rest of the PSOC at speeds up to the selected sample rate. This mode should not be used with multiplexed inputs, because the ADC will not automatically re-prime itself whenever the input is changed. In other words, the values from the previous input will end up getting averaged with the values from the new input, distorting the ADC's output. The user should also note that the first reading will take approximately four times longer than subsequent readings due to the need prime the ADC before valid results are produced. 

  • Multi Sample 
    In this mode, the ADC will continuously generate samples while resetting itself after each valid sample. Thus, this mode is suitable for multiplexed inputs as long as the user either stops the conversion while the inputs are being switched or the inputs are switched very quickly between ADC conversion.  

  • Multi Sample Turbo  
    This mode is identical to the Multi Sample mode except that it provides a sampling rate around four times faster for resolutions from 17 to 20 bit. 

Both the sampling mode and the resolution will affect the sampling rate of the Delta Sigma ADC. Their relation is shown in the graph below: 

          Sigma-Delta Resolution vs Sample Rate

            Graph courtesy of the CY8C58LP datasheet 


 Comparing the resolution of the Sigma Delta and SAR ADC

This example will use the setup from the previous example to compare the resolution of the two different ADCs


  • PSOC 5LP prototyping kit (CY8CKIT-059)
  • Windows PC with PSOC Creator 3.X installed
  • An analog IR distance sensor such as the Sharp Microelectronics GP2Y0A41SK0F
  • IR sensor to servo cable like the one shown here. (makes it much easier to connect the IR sensor to the PSOC)


  1. Begin by opening the SAR Example project used in the previous example.
  2. In PSOC creator, open main.c and modify line sprinf() function so that it reads: sprintf(outputstring, "%9.6f", voltage); 
  3. Build the project and reprogram the PSOC.
  4. Open a terminal program and observe the output. Note the trailing zeros on end of every reading.
  5. In PSOC Creator, open the top design.cysch file
  6. Delete the SAR ADC and replace it with a Delta Sigma ADC. Ensure that Sensor_Pin is connected to the positive input of the ADC.
  7. Double click on the Delta Sigma ADC. Rename it 'ADC'
  8. Under the common tab, the configuration should be: Number of configurations: 1 Clock Source: internal Input Mode: Single ended. The other options should be unchecked except for "External Charge Pump Clock".
  9. Under the Config1 tab, set the resolution to 16 and the voltage range to "Vss to 2.048V (0.0 to x*vref)". Every thing else can remain unchanged.
  10. Rebuild and run the project.
  11. On a terminal program observe the output. Note that, these readings do not have trailing zeros. This is due to the greater resolution of the Delta Sigma ADC.

Digital to Analog Converter: 

The PSOC 5LP contains four 8 bit digital to analog converters. Each of these DACs can be configured as one of the following:

  • Current Output (IDAC)  -  It's maximum conversion rate is 8Msps. Capable of sourcing or sinking currents in ranges of 0 - 32 uA, 0 - 255 uA and 0 - 2.04 mA. 


    IDAC Pin Selection

    Normally, the output of the IDAC can be routed to any GPIO pin. However when using the IDAC in the 2 mA range, it is necessary to route the output to that DAC's dedicated output pin. This is because sourcing that much current through the PSOC's internal analog buses will result in the signal having a significant voltage drop. The IDAC dedicated pins are listed in the table below.

  • Voltage Output (VDAC) - It's maximum conversion rate is 1Msps. Can operate in ranges, 0 - 1.02 V and 0 - 4.08 V. 

  • Dithered Voltage Ouput (DVDAC) - VDAC that utilizes the dithering process, to increase the resolution of the DAC to 9,10 ,11 or 12 bits. Dithering is process of quickly writing several values to the DAC and then averaging the DAC's output. This process effectively increases the resolution of the DAC by several bits. The downside to the dithering process is that it creates additional noise which must be filtered by an off-chip low pass filter. A single capacitor is usually sufficient. 
  • Waveform Ouput (WaveDAC) -This component is a VDAC configured to generate periodic waveforms. The WaveDAC can produce standard sinusoidal, square,triangle and sawtooth waveforms. It can also generate arbitrary waveforms. The arbitrary waveforms can either be drawn manually in the WaveDAC's component configuration window or they can be imported from a file. 

 VDAC Example

This example will demonstrate to the user how to use the VDAC component.


  • PSOC 5LP prototyping kit (CY8CKIT-059)
  • Windows PC with PSOC Creator 3.X installed


  1. Download the unzip the example project: VDAC Example
  2. Connect the PC to the PSOC dev board via USB.
  3. Build the PSOC by selecting the "Build" menu and clicking on the "Build Example" option or alternatively by pressing (shift +F6).
  4. Verify the project builds without errors. Then program the PSOC by selecting the "Debug" menu and clicking on the "Program" option or by pressing ( ctrl + F5).
  5. Use a wire to attach analog Pin 1 to analog Pin 2. In the project, they are configured for ports 3[4] and 3[5] respectively.
  6. Use a terminal program to open up a serial connection with the PSOC. Terminal settings should be: baud rate: 115200, data bits: 8, parity :none, stop bits: 1 and flow control: none.
  7. In the terminal window, the voltage should count up until it reaches about four volts. It should then reset to zero and begin counting again. The output waveform can be verified using an oscilloscope.
 WaveDAC Waveform from file example.

This example will demonstrate how to setup the WaveDAC component to generate a waveform from a .CSV file


  • PSOC 5LP prototyping kit (CY8CKIT-059)
  • Windows PC with PSOC Creator 3.X installed


  1. Begin by opening a text editor that can save .CSV files. Notepad will work just fine.
  2. The WaveDAC is 8 bit so PSOC creator will accept values from 0 to 255 for the WaveDAC and will also accept files with up to 4000 values. However, we'll start with a simple example. In the text file, write the values shown below:
  3. Save the text file as a .CSV file.
  4. Create a PSOC 5LP project or open on that was already created.
  5. In the "Top Design" tab place a WaveDAC component and double click on it to open up its configuration window.
  6. In the configuration window, select "Arbitrary from File" from the Wave Type drop down menu for waveform 1.
  7. Select the .CSV file that you just created.
  8. Once the file is opened, you should see the following waveform in the WaveDAC configuration window. 
  9. Now, reopen the .CSV file in notepad and change the values to the ones shown below:
  10. Save the .CSV file. In the configuration window for the WaveDAC, click on the "..." button next to the Wave Type menu.Select the .CSV file and click "open".
  11. You should see the following waveform in the WaveDAC window.
  12. To utilize the WaveDAC's output, you'll need to route it to an analog pin, In addition, you'll also need to provide either a LOW or HIGH value to the waveform select (ws) pin. A LOW value on this pin means that WaveDAC will output waveform 1 and a HIGH value on the ws pin will output waveform 2. An example configuration for outputting waveform 1 is shown below:
  13. The final step in order to use the WaveDAC is to ensure that the WAVEDAC_Start() function is called in Main.c


Op-amps are devices used for amplifying and buffering voltage signals. The PSOC 5LP has four standalone op-amps that can be configured as either gain blocks or voltage followers. In order to use the op-amps as a gain block, off chip resistors will need to be used. These op-amps can be used to amplify either off chip signals or signals originating inside the PSOC. 

The user is able to change the op-amps power modes in order to optimize power usage at the expense of the op-amp's bandwidth. A summary of the power modes is shown below:

High powerLargest bandwidthOp-amp is capable of driving up to about 25 mA ouput current
Medium powerMedium bandwidthAlso capable of driving up to around 25 mA output current
Low powerLowest bandwidthUnable to drive significant output current.
Low Power Over CompensatedLowest bandwidth

Same as low power, except the output is compensated

in order to better drive transimpedance (TIA) amplifiers

Even though these components do not utilize the processor to operate, the user still needs to initialize and enable them by calling the Opamp_Start() function in the main.c file.

OP-AMP Pin selection

Some special considerations should be taken when selecting GPIO pins for the PSOC 5LP's op-amps. 

  • If the inputs for the op-amp are connected to an external source, the user should use that op-amp's dedicated GPIO pins. For example, Opamp0 uses pins P0[2] for its non-inverting input and P0[3] for its inverting input.  The reason for this is because the connections between the op-amps and their dedicated GPIO pins bypass several of the PSOC's internal analog buses, thus providing the lowest impedance path between the op-amps and the outside world.   
  • if the op-amp is being used internally, the op-amps dedicated input pins can either be ignored or used for another purpose. 
  • The op-amps dedicated output pin is always connected to the op-amps output. This means that even if the op-amp is being used internally, the output signal will still appear on the op-amps dedicated GPIO. Therefore, if an op-amp is being used, its dedicated output pin should not be used for any other purpose.  
  • The op-amps' dedicated pins are listed in the table below:


Op-AmpNon-Inverting InputInverting inputOutput


Opamp1 P3[5]P3[4]P3[6]




A comparator is a device that is used to indicate if one voltage is larger than another. The way it operates is quite simple, when the voltage on the positive input is larger than the voltage on the negative input, the comparator will output a high signal. Likewise when the negative input is larger than the positive input, the comparator will output a low signal. A typical configuration will have a reference voltage connected to the negative input and the signal that's being compared connected to the positive input. 

The PSOC 5LP contains four discrete comparators. These comparators have the following configuration options:

  • Hysteresis -  When hysteresis is enable, feedback is established between the comparator's output and inputs which results in 10 mV voltage threshold between the inputs. In other words, when hysterisis is enabled, there must be at least a 10 mV  difference between the input voltages in order for the output to change. This setting prevents the output of the comparator from oscillating due to a noisy input voltage. 
  • Speed - This option allows the user to change the speed of the comparator in order to optimize power use. The speed options are listed below: 
        1. Fast:                             For response times > 80 nanoseconds 
        2. Slow:                             For response time <  80 nanoseconds 
        3. Ultra Low Power :         Lowest power mode, slowest response time
  • Polarity - This allows the user to invert the output of the comparator. Essentially, the output of the comparator is sent through a NOT gate created using one of the PSOC's universal digital blocks. 
  • PowerDownOveride- This option will keep the comparator active when the PSOC is in sleep mode. It should be noted that the polarity of the comparator cannot be set to inverted output when this option is selected since the UDB's are disabled in sleep mode. 
  • Sync - This allows the comparator's output to be synchronized to a bus clock. When this option is selected, the comparator output will only change on the rising edge of a clock pulse. 


 Window Comparator Example

 This example demonstrates how to implement a simple window comparator circuit on the PSOC 5LP. A window comparator is used to determine if a input voltage is within certain voltage range. This example's schematic is shown below.

The analog input pins, comparators and digital output pins are all connected internally within the PSOC. The output pins (Pin_1 and Pin_2) need to be connected to each other externally. In addition the output pins also need to be attached to the positive voltage supply via a pull-up resistor.

When the input voltage is greater than VLOW and smaller than VHIGH both the comparators will drive their respective output pins high which will result in the output being high. When the input voltage falls below VLOW, Comp_2 will drive Pin_1 low which will in turn drive the Output low. Likewise, when the input voltage exceeds VHIGH, Comp_1 will drive Pin_2 low which in turn will drive the output low. To state it simply, the circuit produces a high output when input voltage is within the voltage limits and a low output when it is outside the voltage limits.


  • PSOC 5LP prototyping kit (CY8CKIT-059)
  • Windows PC with PSOC Creator 3.X installed
  • Power supply(s) capable of generating the required input and trip point voltages.
  • A digital multimeter
  • Discrete 10 Kohm resistor


  1. Download and unzip the example project: Comparator Example
  2. Open the project. On the left have of screen, in the workplace explorer window, double click on the "Window Comparator Example.cycdwr" file
  3. This will open the pin selection screen. Route the pins to whatever GPIOs are the most convenient.
  4. Connect the PSOC 5LP prototyping kit to the pc via USB.
  5. Build the project by selecting the "Build" menu and clicking on the "Build Example" option or alternatively by pressing (shift +F6).
  6. Verify the project builds without errors. Then program the PSOC by selecting the "Debug" menu and clicking on the "Program" option or by pressing ( ctrl + F5).
  7. Unplug the PSOC 5LP prototyping kit from the pc.
  8. Connect digital output pins to each other, then use the 10K resistor to connect the output pins to a positive voltage.
  9. Attach a digital multimeter to one of the output pins. Set the meter to measure a DC voltage between 0 and 5.5 volts.
  10. Important! Ensure that none of the voltage sources exceed 5.5 volts. If more than 5.5 volts are applied to the PSOC, it will be damaged.
  11. Attach the VHIGH, VLOW and Input voltage sources to the PSOC 5LP prototyping kit. The PSOC will need to be powered as well, this can be accomplished by attaching a voltage source to the VDD pin on the prototyping kit. 
  12. Adjust the input voltage while monitoring the multimeter. You should notice that that the output remains high while the voltage input is between VHIGH and VLOW and that the output is low when the voltage input exceeds either of those limits.

Like the Op-amp, the comparator will not function if the user doesn't call the Comp_Start() function in main.c



Switched Capacitor/Continuous Time (SC/CT) blocks: 

The SC/CT blocks each consist of a single high bandwidth op-amp connected to series of switches and capacitors. By switching in and out the various resistors and capacitors, the user is able to create different analog functions. 

PSOC creator can create the following components out of the (SC/CT) blocks. 

Programmable Gain Amplifier (PGA):    

This component is a op-amp configured in the non-Inverting amplifying topology. Unlike the  PSOC's discrete op-amps, this amplifier does not require external resistors. The user is able to adjust the gain of the amplifier either via the PGA component's configuration window or by calling the PGA_SetGain() function in software. It should also be noted that as the gain of the PGA is increase, its bandwidth will decrease.                                                                                

Inverting PGA:                                         

Same as the PGA component, but utilizes the Inverting amplifier topology. 


Trans-Impedance (TIA) Amplifier:            

This amplifier is used to convert a current signal into a voltage signal. Unlike the PGAs where only the gain can be adjusted, here the user is able to individually configure both the feedback resistance and feedback capacitance to get the desired amplifier gain and bandwidth.  



 A mixer takes a time-varying input signal and combines it with another alternating signal to create new signals at a different frequency. Typically, one of the input signals will be a known reference signal. This signal is referred to as the Local Oscillator (LO) signal. For the mixers on the PSOC, the LO signal is a clock signal that is provided by either a system clock or external source. In addition to the desired output signal, the mixer will also produce several other signals at various frequencies.To filter out these unwanted signals, the mixer's output will need to be routed through an off-chip filter.

The SC/CT block supports two mixer architectures, the Multiplying and the Sample and Hold.

  • Multiplying Mixer- Also referred to as the "UP mixer" in PSOC creator. The output frequency of this mixer can be calculated by the equation: Fout = N*Flo ± Fin where N is an odd number. This equation shows that this mixer will not only create output signals at (Flo + Fin) and (Flo - Fin), but that it will also create signals at every odd harmonic of the LO signal plus and minus the input frequency. The multiplying mixer supports input signals of up to 500 kHz and LO frequencies of up to 1MHz. 

  • Sample and Hold Mixer-Also referred to as the "Down mixer" in PSOC creator. This mixer utilizes the switching capacitor architecture to sample and convert the incoming waveform. It's output frequency is defined by the equation Fout = abs(N*Flo-Fin). The sample and hold mixer supports input frequencies of up to 14 MHz and LO frequencies of up to 4 MHZ. 


Reference Voltage: 

This component is a stable analog voltage source that changes very little with variations in temperature and the PSOC's supply voltage. It is available as either a 1.024 V or 0.256 V source. Alternatively, this component can be used to connect one of the PSOC's voltage pins, such as Vbat, or internal voltages, like VSSa, to components within the PSOC. This component works well wherever an accurate reference is needed such as the reference input for a comparator. This component should not be used to source or sink current as that will affect the accuracy of the voltage source.  

Comparator circuit using the reference voltage component.


Additional Notes on Analog Pin Selection: 

The PSOC 5LP silicon die is essentially comprised of two sections, the analog section and the digital section. Three of the PSOC 5LP's ports reside in the analog portion of the chip, P0[7:0], P3[7,0] and P4[7,0]. Analog signals on these ports will have a slightly better signal to noise ratio than signals on other ports due to their close proximity to the analog section. 

In mixed signal designs, signals on the digital lines can capacitively couple into analog lines, distorting the analog signals. In order to prevent coupling between pins, as well as reduce the amount of cross talk that occurs within the PSOC itself, at least one unused pin should separate the analog GPIO pins from the digital ones. Ideally, the pins for the analog signals and the pins for the digital signals should be located on opposite ends of the chip. 

Additional information about selecting and routing analog pins can be found in the Cypress app note AN58304 which can be found in the useful links section of this article. 


Contacting the Author: 

Hopefully this article helped you become acquainted with the analog capabilities of the PSOC 5LP. The user is free to use the examples in their own projects and can modify them as they see fit. If you have any comments or questions about the article, you can reach me at

-Matthew Bon 

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