Child pages
  • Frequently Asked Questions - Embedded Systems Design
Skip to end of metadata
Go to start of metadata


The purpose of this page is to address some commonly asked questions regarding embedded systems design.  Some of the presented questions are broad or conceptual in nature.  Others are more narrow in focus and may pertain to a single peripheral within a microcontroller.  After you have browsed through the various topics, please take a moment to visit the various spaces within the eewiki.  You will find some hands-on examples incorporating the topics discussed below.



What is an Embedded System?

An embedded system is comprised of hardware and software with a dedicated function and is part of a larger system.  Normally it includes one or more microprocessors or microcontrollers which supervise system functions.  An embedded system incorporates some sort of software that automatically boots on power-up.  Many times, the software will run autonomously.  However, it is not uncommon for an embedded system to include some sort of user interface for external control and monitoring (buttons, switches, LEDs, LCDs, etc).

What is a Microprocessor?

A microprocessor performs all functions of a Central Processing Unit and is manufactured into a small integrated circuit.  It interprets and executes program instructions and can be thought of as "the brain" of an embedded system.  It includes digital logic that executes instructions in a specific order.  A master clock is used to continue executing instructions in sequential order.  It's not uncommon for the master clock to be divided internally into individual clock signals that trigger specialized hardware sections.

What is a Microcontroller?

A microcontroller integrates a CPU with memory and hardware peripheral circuitry that serve specific purposes. 

For memory, a microcontroller includes some sort of non-volatile programmable memory that becomes Read-Only at run-time.  This memory is where the user would program application code which executes instructions in a specific order to achieve the system's overall purpose.  A microcontroller usually has volatile Random Access Memory that can be used at run-time for manipulating variables and storing results.  Sometimes a microcontroller will include extra non-volatile memory for storing information while powered-down.

The dedicated hardware peripherals will vary depending on the microcontroller.  Some common hardware peripherals include timers, serial communication blocks, analog to digital converters, digital to analog converters, analog comparators, and general purpose input and output pins.

What is the difference between parallel and serial communication?

When two devices communicate with each other, it means they are exchanging data.  The system architecture will define the number of bits each data word is made up of, but 8, 16, and 32-bit data words are probably the most common.  Parallel communication uses a dedicated wire for each bit in the data word.  Serial communication on the other hand, shifts all bits onto a single data line in some predefined order.  Typically, serial communication will use a single data line and shift each bit in sequential order, either most significant bit (msb) or least significant bit (lsb) first.  However, some serial protocols will rearrange the bits in non-sequential order to mitigate electrical effects (DC offset, EMI, etc.) on the rest of the board.

The major benefit of using Parallel communication is that it takes less clock cycles to transmit the same amount of data as serial communication would.  For example, if 8 individual lines were used to transmit an 8-bit data word, the entire data word would be transmitted in a single clock cycle.  Compare that to a serial communication protocol that uses a single data line.  It would take 8 clock cycles to transmit the same data word.

The major benefit of using Serial communication is that it takes far less pins on a device and less board space for running trace wires.  This allows the pins to be used for other purposes, and generally reduces the required board space and/or cable size.

Hybrid communication protocols also exist which make use of the advantages of each.  For example, dual and quad I/O SPI protocols use more than one serial data pin to increase overall bandwidth.  Ultimately, it's up to the designer to understand the tradeoffs and determine what is required/acceptable for a specific application.

What is the difference between synchronous and asynchronous communication?

Synchronous communication means that the two (or more) devices exchanging data share a common clock line.  One device (typically referred to as the Master) will drive the clock signal as an output, while the other device (typically referred to as the Slave) will read the clock signal as an input.  As the name suggests, this keeps the devices synchronized and ensures data is setup and sampled at the correct times.  The major benefit of synchronous communication is that it is reliable.  You don't need to worry about setting up accurate reference clocks on each device to achieve the appropriate baud rate and temperature has little or no effect on data reliability.  The down side is that it takes an extra pin, and generally increases the required board space/cable size.  Running a clock signal on a board can also increase EMI effects.

Asynchronous communication means that the two devices do not share a dedicated clock signal...a unique clock exists on each device.  Each device must setup ahead of time a matching bit rate and how many bits to expect in a given transaction.  Asynchronous communication is nice because it takes one less pin, which saves board space/cable size, and allows the designer to use that pin for other purposes.  Removing a clock line from a board also helps reduce EMI.  The downside to using asynchronous communication is that it is more difficult to achieve reliable communication.  The reference clocks used for generating the bit rate must be fairly accurate and stable over temperature or timing could get thrown off.  Integer drop-off can also introduce error in the baud rate.  This occurs when you try and achieve a baud rate that is not an exact integer multiple of the reference clock.  In other words, even with a perfect reference clock, the desired baud rate may not be achievable without a certain amount of error.  The amount of error may or may not be acceptable.

What is I2C?

The Inter-Integrated Circuit (I2C) protocol is a very popular synchronous serial communication protocol in embedded designs due to the low number of pins required and the large number of devices that can be connected to a single bus.  A single data line (SDA) and a single clock line (SCL) plus common ground are the only required connections between an I2C master and slave.  The following figure (taken from the I2C wikipedia page) shows a simplified timing diagram for I2C transactions.  The first yellow box indicates a START signal.  A START condition is the only time the SDA line will transition low while the clock line is high.  During the transcaction, SDA transitions are made while SCL is low (blue) and SDA is sampled while SCL is high (green).  The second yellow box indicates a STOP signal.  A STOP condition is the only time the SDA line will transition high while the clock line is high.  Open-drain outputs with external pull-up resistors are used for the data and clock lines.  Once a device stops actively driving the bus lines, the external resistors pull each line high.

I2C Timing Example

I2C is an address-based protocol, meaning each slave device has a unique I2C address.  I2C supports multiple masters and multiple slaves on a single bus.  A device's datasheet will specify its I2C slave address.  Typically, a device will use a 7-bit I2C slave address, although some variations to the I2C protocol also support 10 and 16-bit addressing modes.  A typical I2C transaction would begin with a master issuing a START signal, followed by a single byte consisting of the slave's 7-bit address and a single read/write bit.  After the slave address byte, the message format varies a bit from device to device.  There is no limit to the number of bytes that can be transmitted in a single transaction.  However, each byte must be acknowledged by the receiving device before the next byte is sent.  After the last byte and acknowledge is received, the master will end the transaction by issuing a STOP signal.  For devices that support larger addressing schemes, the initial byte format may also change.  The specific device's datasheet will describe the required I2C message format.  100kbps is the standard I2C data rate while more recent I2C variations support 400kbps fast mode, 1Mbps fast mode plus, and 3.4Mbps high speed mode.

What is SPI?

The Serial Peripheral Interface (SPI) protocol is another popular synchronous serial communication protocol in embedded designs.  SPI communication involves one or more master devices and one or more slave devices using a shared bus.  Full duplex or 4-wire SPI uses two data lines, a shared clock line, and a slave select line.  Half duplex or 3-wire SPI uses a shared data line.

Pin Descriptions

  • MISO:  Master In, Slave Out  -  Data is shifted out from the slave and into the master on this line.
  • MOSI:  Master Out, Slave In  -  Data is shifted out from the master and into the slave on this line.
  • SCLK:  Clock  -  The clock is always driven by the master.  The clock starts as soon as data is loaded into the master's transmitter and stops when the last bit is shifted out.
  • SS:  Slave Select  -  A dedicated slave select (or chip select) line is used to address different slave devices.  A slave will only receive data if its SS pin is asserted (active low).

SPI Timing

The following figure was taken from an Atmel Xmega-A3U manual.  It illustrates the 4 SPI modes of operation.  The 4 modes are similar for all SPI devices.

  • Mode 0:  SCLK idles low. Data is setup on falling edge of SCLK.  Data is sampled on rising edge of SCLK.
  • Mode 1:  SCLK idles low. Data is setup on rising edge of SCLK.  Data is sampled on falling edge of SCLK.
  • Mode 2:  SCLK idles high. Data is setup on rising edge of SCLK.  Data is sampled on falling edge of SCLK.
  • Mode 3:  SCLK idles high. Data is setup on falling edge of SCLK.  Data is sampled on rising edge of SCLK.

General Operation

The master always initiates transmission.  The slave simply has to wait for its SS line to be asserted and the SCLK to appear, or prompt the master using other I/O.  When SCLK activates, data will simultaneously start shifting out on the MOSI line and in on the MISO line.  Data gets shifted in/out one bit at a time until every bit has been shifted.  Usually a microcontroller will have a built in SPI register that sets a flag when all data bits have been shifted out.


  • Low overhead - SPI protocol uses dedicated slave select lines for each slave device.  This eliminates the need for sending addresses over the data lines and decreases overhead.
  • Reliable - The dedicated clock line eliminates baud mismatches that are common in asynchronous protocols (like UART).
  • Fast - Dual data lines increase the overall throughput and the low overhead increases overall bps.
  • Shared bus - The dedicated slave select lines allow multiple devices to share the same data/clock lines.  If the device's SS line is not enabled, the device will simply ignore data.


  • High pin count - Compared to other common serial communication protocols, SPI uses quite a few pins.  An extra pin (SS) is required for every slave device and master device for multi-master setups.
  • Error checking - No default CRC checking or bus contention indication
  • Transmission Initiation - The master must initiate all transmissions.  If a slave has data to send to the master, it must wait for the master to start transmission, or use external signals to interrupt the master.

What is a UART?

A Universal Asynchronous Receiver/Transmitter (UART) is a very simple method of serial communication in embedded designs.  UART communication in full-duplex mode uses one pin for Transmit (TX) and one pin for Receive (RX).  Half-duplex uses a shared pin for TX and RX (commonly referred to as single-wire UART or 1-wire Comm).  Both versions require a common ground to operate properly since TX and RX are single-ended signals.

Since there is no shared clock line, the data rate and frame format need to be setup on both ends of the communication link ahead of time.  7, 8, and 9-bit data frames are common lengths with 8-bit being the most prevalent.  The data lines will idle high between transmissions.  There is no master-slave relationship in the UART protocol, therefore either device can initiate transmission.  This is accomplished by driving the transmit pin low for one bit-period (considered a START signal).  The specified number of data bits will follow, typically transmitted least-significant-bit first.  An optional parity bit can be used for basic error checking.  The parity bit is used to make the "sum" of the data bits even or odd and gets transmitted along with the data.  The receiver will recalculate the sum of the data bits and parity bit and compare to the expected parity as a simple check for data integrity.  The frame is ended by driving the line high for the specified number of bit periods (STOP bits).  The receiver on each end uses oversampling to read each bit of incoming data.  The oversampling rate is dependent on the desired baud rate being used.

The following image was taken from an Atmel ATmega256RFR2 datasheet (Sec 23.4).  It shows the frame format for UART communication.

Separate flow control signals Clear-To-Send (CTS) and Request-To-Send (RTS) are sometimes utilized to provide more efficient transactions between devices that operate at different speeds.  This is especially common when mixing electrical systems with mechanical systems (for example a desktop printer).  The electrical signal takes very little time to complete.  However, the mechanical motion of a motor or solenoid will take much longer to complete a process.  The two devices would most likely use CTS and RTS signals in a handshaking method to make sure data is transmitted at the proper times.

What is a USART?

A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is a dedicated hardware peripheral found in some microcontrollers.  The USART peripheral gives the user the option of using synchronous or asynchronous communication.  It can be used as a UART as described above utilizing only data lines, or it can be used in synchronous mode which will add the clock line.  Synchronous mode will generally allow for burst transactions (sending multiple bytes in a single transaction) whereas asynchronous mode generally sends a single byte at a time.  Most microcontrollers that contain a USART will allow the user to implement the SPI protocol on it (in synchronous mode).  However, it should be noted that most microcontrollers that support USART SPI mode typically don't support SPI slave mode on the USART, only SPI master mode.  Basically, a USART gives you the ability to implement UART or SPI without restricting you to one or the other. 

What is an ADC?

An Analog to Digital Converter (ADC) is one of the most common peripherals found in microcontrollers.  An ADC converts a continuous analog voltage, at a single point in time, to a digital value that can be interpreted by a digital device, such as a microcontroller.  The designer decides how frequently to sample the analog signal.  However, every ADC has a maximum sampling rate that cannot be exceeded. 

The resolution is another important ADC spec.  The resolution defines the number of bits used to describe the analog signal at a given point in time.  8, 10, and 12-bit are typical ADC resolutions available in inexpensive microcontrollers.  Some special purpose ADC's even go as high as 32-bits of resolution.  The more resolution you have, the finer you can define an analog signal.  For example, an ADC with 10-bits of resolution will allow for 2^10 or 1024 possible digital values that can be used to describe the analog signal.  A 16-bit ADC on the other hand will allow for 2^16 or 65,536 individual digital values that can be used to represent the analog signal. 

The analog input range of the ADC is another important thing to consider.  For single-ended measurements (measurements taken with reference to ground), the analog input range is generally from 0V up to the defined reference voltage.  Normally, the designer has options when it comes to selecting a reference voltage.  Differential measurements sample two different analog signals and take the difference between the two.  This is useful in eliminating external noise that is present on both signals, known as common-mode noise.

What is a DAC?

A Digital to Analog Converter (DAC) converts a digital signal to a continuous analog signal.  DAC's are typically used in audio applications to drive a speaker or amplifier.  Similar to an ADC, a DAC will have a maximum operating speed that cannot be exceeded.  A DAC will also have a fixed resolution as an ADC does.  A higher resolution will allow for finer control over the analog output.

A DAC will take a digital input and create a single pulse up to the specified analog value.  As you input a stream of digital values to the DAC, you will get subsequent pulses of analog output.  The spaces between the output pulses will be interpolated by a filter to achieve a continuous signal.  As previously stated, DACs are typically used in audio applications.  Therefore, the digital inputs are usually applied at constant time intervals and the analog output is updated accordingly.

What is Pulse Width Modulation?

Pulse-Width-Modulation (PWM) is a method of controlling a voltage or current by varying the signal between fully ON and fully OFF and precisely controlling the amount of time spent in each state.  The pulse train is switched at a constant frequency and the average value of the signal is directly proportional to the ratio of ON/OFF time.  This ON/OFF time ratio is known as duty cycle.  Duty cycle allows us to think in terms of percentage rather than individual units of time.  Let's take a look at a simple example.

The following image shows a PWM signal with 50% duty cycle, meaning the signal is ON 50% of the time and OFF 50% of the time.  If the signal is being switched between 0 and 5V for example, the average value of the following PWM signal would be 2.5V.

In this next image, the duty cycle is increased to 75%, meaning the signal is ON 75% of the time and OFF 25% of the time.  This increases the voltage from 2.5V to 3.75V (75% of 5V).

It should be noted that the period (frequency) of the PWM signal remains constant.  You can see in both images that the black lines are evenly spaced and that the falling edge of the signal always occurs at a defined time.  The rising edge, and hence the pulse width, is what we are adjusting to precisely control the average value.  The required switching frequency will be application specific.

PWM is used extensively in embedded designs.  Motor control, LED intensity control, and DC/DC power conversion are all typical applications for Pulse Width Modulation.

What is DMA?

Direct Memory Access (DMA) allows a device, such as a microcontroller to perform certain tasks without using the CPU.  The DMA controller can supervise tasks and transfer data between different areas of memory.  This allows the CPU to perform other tasks while waiting for slower functions to complete.  This increases throughput and overall program execution efficiency.




  • No labels