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Introduction

This introduction into the Digilient Arty A7 (35T and 100T) FPGA Evaluation Kit walks through implementing SiFive's FE310 RISC-V on Xilinx Artix-7 FPGA's.  Topics include connecting a JTAG, installing Vivado, building the FE310 bitsream, programming the on-board configuration memory, and running example FE310 projects.

Hardware Requirements


Arty A7-35TArty A7-100T
FPGA partXC7A35TICSG324-1LXC7A100TCSG324-1
1 MSPS On-chip ADCYesYes
Logic Cells33,280101,440
Logic Slices5,20015,850
Flip-flops29,20065,200
Block RAM (Kbits)1,8004,860
DSP Slices90240
Clock Management Tiles56
GTP 6.6Gb/s Transceivers48
I/O Pins250300

Vendor Documentation


Hardware Setup

Arty Board JD Header

TDOTDI
nTRSTTMS
TCKnRST
78
GNDGND
VREFVREF

Olimex ARM-USB-TINY-H

VREFVREF
nTRST4
TDI6
TMS8
TCK

10

1112
TDOGND
nRSTGND
1718
1920



Software

Install Vivado 2017.01

This project requires Vivado Design Suite 2017.01, download the WebPACK Edition

/opt/Digilent/
sudo chmod +x Xilinx_Vivado_SDK_2017.1_0415_1_Lin64.bin
./Xilinx_Vivado_SDK_2017.1_0415_1_Lin64.bin



  • Select the Vivado HL WebPACK option:


  • Make sure the 7 Series (Artix-7) is selected:


  • Install to the Common Build Directory for this project: (/opt/Digilent/Xilinx)


  • Summary

Install Digilent system board files for Vivado

Download the Digilent repository that contains system board files for Vivado. Once downloaded these can been be copied to the Vivado board_files directory.

/opt/Digilent/
git clone https://github.com/Digilent/vivado-boards
cp -rv ./vivado-boards/new/board_files/* /opt/Digilent/Xilinx/Vivado/2017.1/data/boards/board_files/

Install prebuilt RISC-V Toolchain

Download GNU Embedded Toolchain and OpenOCD from: https://www.sifive.com/boards

/opt/Digilent/
wget -c https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
wget -c https://static.dev.sifive.com/dev-tools/riscv-openocd-0.10.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz

Extract GNU Embedded Toolchain and OpenOCD

/opt/Digilent/
tar xf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
tar xf riscv-openocd-0.10.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz

Double Check that GCC and OpenOCD work on your system

/opt/Digilent/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version
riscv64-unknown-elf-gcc (GCC) 8.1.0
Copyright (C) 2018 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
/opt/Digilent/riscv-openocd-0.10.0-2018.12.0-x86_64-linux-ubuntu14/bin/openocd --version
Open On-Chip Debugger 0.10.0+dev-gcd32bd4 (2018-12-19-01:15)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html

Install udev rule for Olimex JTAG

Olimex udev rule:

/etc/udev/rules.d/99-openocd.rules
SUBSYSTEM=="tty", ATTRS{idVendor}=="15ba",ATTRS{idProduct}=="002a", MODE="664", GROUP="plugdev"
SUBSYSTEM=="usb", ATTR{idVendor}=="15ba",ATTR{idProduct}=="002a", MODE="664", GROUP="plugdev"

Double check permissions:

ls -lha /dev/ttyUSB0 
crw-rw-r--+ 1 root plugdev 188, 0 Feb  8 14:12 /dev/ttyUSB0

Download the SiFive Freedom repository

This repository contains the SiFive RTL for the Freedom E300 and U500 platforms.

/opt/Digilent/
git clone --recursive https://github.com/sifive/freedom
cd freedom/

Building for the Artix-7 35T or 100T

export RISCV and VIVADO for the project's Makefile

/opt/Digilent/freedom/
export RISCV=/opt/Digilent/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14
export PATH=/opt/Digilent/Xilinx/Vivado/2017.1/bin:$PATH


Building Artix-7 35T
make BOARD=arty -f Makefile.e300artydevkit clean
make BOARD=arty -f Makefile.e300artydevkit verilog
make BOARD=arty -f Makefile.e300artydevkit mcs
Building Artix-7 100T
make BOARD=arty_a7_100 -f Makefile.e300artydevkit clean
make BOARD=arty_a7_100 -f Makefile.e300artydevkit verilog
make BOARD=arty_a7_100 -f Makefile.e300artydevkit mcs

For Reference, this build is based on:

voodoo@hades:/opt/Digilent/freedom$ git show
commit 3624efff1819e52cec30c72f9085158189f8b53f (HEAD -> master, origin/master, origin/HEAD)
Merge: 2dd298f 959683b
Author: erikdanie <43764516+erikdanie@users.noreply.github.com>
Date:   Thu Oct 18 14:07:44 2018 -0700

    Merge pull request #93 from sifive/bump-submodules
    
    Bump submodules

Vivado Installing Configuration to Device

Connect both Olimex USB JTAG and ARTY's J10 USB interface. (J10 is also the default uart on the FE310)


  • Open Vivado 2017.1
  • Flow → Open Hardware Manager
  • Open Target → Auto Connect

  • Right Click device → Add Configuration Memory Device

35t100t
ManufacturerMicronSpansion
Density (Mb)128128
Typespispi
Widthx1_x2_x4x1_x2_x4
Aliasn25q128-3.3v-spi-x1_x2_x4s25fl127s-spi-x1_x2_x4

Load *.mcs file: /opt/Digilent/freedom/builds/e300artydevkit/obj/E300ArtyDevKitFPGAChip.mcs

The "PROG" button the Arty A7 can be used reload the configuration file onto the Artix-7.

SiFive Freedom E SDK Examples

/opt/Digilent/
git clone --recursive https://github.com/sifive/freedom-e-sdk.git
cd freedom-e-sdk/

Set RISCV_PATH and RISCV_OPENOCD_PATH

/opt/Digilent/freedom-e-sdk/
export RISCV_PATH=/opt/Digilent/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14
export RISCV_OPENOCD_PATH=/opt/Digilent/riscv-openocd-0.10.0-2018.12.0-x86_64-linux-ubuntu14

For reference, this build is based on:

voodoo@hades:/opt/Digilent/freedom-e-sdk$ git show
commit 30837cf2279ec60989898a0d8ef5a1934bd443c0 (HEAD -> master, origin/master, origin/as-eclipse-project, origin/HEAD)
Merge: 4c20f51 8565ab5
Author: Nathaniel Graff <nathaniel.graff@sifive.com>
Date:   Wed Feb 6 19:15:22 2019 +0000

    Merge pull request #169 from sifive/documentation
    
    Add initial documentation

Example hello

/opt/Digilent//freedom-e-sdk/
make BSP=metal PROGRAM=hello TARGET=freedom-e310-arty clean
make BSP=metal PROGRAM=hello TARGET=freedom-e310-arty software
make BSP=metal PROGRAM=hello TARGET=freedom-e310-arty upload
make BSP=metal PROGRAM=hello TARGET=freedom-e310-arty upload
scripts/upload --elf /opt/Digilent/freedom-e-sdk/software/hello/hello --openocd /opt/Digilent/riscv-openocd-0.10.0-2018.12.0-x86_64-linux-ubuntu14/bin/openocd --gdb /opt/Digilent/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gdb --openocd-config bsp/freedom-e310-arty/openocd.cfg
Open On-Chip Debugger 0.10.0+dev-gcd32bd4 (2018-12-19-01:15)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Info : datacount=1 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 1 harts
Info :  hart 0: XLEN=32, misa=0x40001105
Info : Listening on port 3333 for gdb connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333
Info : Found flash device 'micron n25q128' (ID 0x0018ba20)
metal_shutdown (code=0) at /opt/Digilent/freedom-e-sdk/freedom-metal/src/shutdown.c:19
19	      __asm__ volatile ("nop");
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
cleared protection for sectors 64 through 255 on flash bank 0
cleared protection for sectors 64 through 255 on flash bank 0
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Loading section .init, size 0x56 lma 0x20400000
Loading section .text, size 0x3daa lma 0x20400080
Loading section .rodata, size 0x6a0 lma 0x20403e2c
Loading section .eh_frame, size 0x7c lma 0x204044cc
Loading section .init_array, size 0x4 lma 0x20404548
Loading section .data, size 0x17bc lma 0x2040454c
Info : Padding image section 0 at 0x20400056 with 42 bytes
Info : Padding image section 1 at 0x20403e2a with 2 bytes
Info : Disabling abstract command writes to CSRs.
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Start address 0x20400000, load size 23772
Transfer rate: 22 KB/sec, 3396 bytes/write.
shutdown command invoked
shutdown command invoked
A debugging session is active.

	Inferior 1 [Remote target] will be detached.

Quit anyway? (y or n) [answered Y; input not from terminal]
Remote connection closed
voodoo@hades:~$ tio /dev/ttyUSB2  -b57600
[tio 14:08:39] tio v1.32
[tio 14:08:39] Press ctrl-t q to quit
[tio 14:08:39] Connected
Hello, World!
Hello, World!

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