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It wasn’t long ago that embedded design teams simply accepted the fact that they would have to do without hardware floating-point support in microcontroller (MCU)-based systems. But a designer considering a new project should forget that ingrained notion. Moore’s Law has made it possible for MCU vendors to integrate floating-point units (FPUs) on mainstream products and still deliver a cost-effective die size. Moreover an accelerated design cycle and an easier embedded code base can overshadow the cost premium associated with an FPU-enabled MCU in many applications.
Floating-point math is important in a host of applications such as motor control. Even seemingly simple applications in which a control system monitors a sensor, such as a thermocouple, can require floating-point math. As most design engineers know, the relationship between temperature and a thermocouple’s output voltage is not linear. To get an accurate temperature measurement, a program that reads the sensor must calculate a complex polynomial equation that is most easily handled with floating-point math.
Design teams regularly prototype such applications using a PC platform and in doing so rely on floating-point math. Using floating-point math eliminates the scaling and shifting operations that are a requisite in handling a floating-point problem on a fixed-point processor. Relying on floating-point math greatly accelerates and simplifies the development process and avoids the potential errors that can creep into floating-point algorithms developed for a fixed-point execution environment.
But what happens when the code is moved to a target processor that lacks an FPU? The design team has several options. Perhaps the simplest path is a floating-point library. Such libraries are available from MCU and development-tool vendors and offer an easy way to convert floating-point instructions into simple function calls to the floating-point routines in the library.
Unfortunately the library route can impact the performance of the system and the size of the embedded code. Renesas has published a use case for their RX MCU that evaluates the impact of calculating a fifth-order polynomial with a library using fixed-point math. The calculation adds more than 1,500 bytes of code and takes 134 µs to execute on a 100-MHz processor.
In some cases, the design team may find that the code size and performance impacts of a library are not an adverse factor based on the application at hand. In other cases, the design team will have to come up with a faster solution and/or one with a smaller code footprint.
Traditionally, most design teams have undertaken the time-consuming process of hand-optimizing routines that handle floating-point operations using fixed-point math. But an MCU with an FPU solves the problem entirely. And today design teams will find a broad choice of MCUs with integrated FPU support.
Renesas, for example, did include an FPU in the design of their new flagship RX MCU. In the thermocouple example mentioned earlier, the RX can handle the fifth-order polynomial with native floating-point math in 7 µs using 38 bytes of code.
Design teams that want to use ARM architecture and also have emerging MCU choices with FPUs. STMicroelectronics, for example, recently announced that it will offer MCUs based on the Cortex-M4 core that will include both an FPU and support for DSP functions. The company plans to offer the MCUs as part of the STM32 family and the new MCUs will be manufactured as pin-compatible extensions to the STM32 MCUs that until now have been based on the Cortex-M3 core. In fact the company will also offer lower-end pin-compatible MCUs based on the Cortex-M0 core.
NXP has already announced four families of Cortex-M4-based MCUs that integrate FPUs. The MCUs are unique in that the LPC4310, 4320, 4330, and 4350 MCUs integrate both a Cortex-M4 core for maximum math performance and a Cortex-M0 core to handle system-management functions. Texas Instruments (TI) is also a supplier of ARM-based MCUs, but at press time had not announced any such products with FPUs. But TI does offer its TMS320F283xx family of 32-bit Delfino MCUs with an integrated FPU. The FPU-enabled MCUs are part of the company’s C28x-core family that includes a broad range of performance options in a software-compatible family.
Renesas actually offers FPU support in several MCU architectures. For example, the company recently announced the SH7268 and SH7269 in the SuperH family. The MCUs target applications such as digital audio, auto infotainment, and industrial applications. Moreover, the V850 family that came to Renesas in the recent merger with NEC Microelectronics also includes MCUs with integral FPUs.
Expect the FPU trend to escalate and even move downward into lower-performance architectures going forward. As MCU vendors move to finer semiconductor process nodes, integrating an FPU is more easily justified. And as design teams move away from hand coding performance-intensive routines such as floating-point algorithms, the value of an FPU escalates. Even today, teams should closely consider the real impact in terms of performance and code size before considering a fixed-point MCU.
About the Author
Maury Wright is an electronics engineer turned technology journalist and industry consultant with broad experience in technology areas ranging from microprocessors to digital media to wireless to power management. Wright worked at EDN Magazine for 22 years, serving as editor-in-chief and editorial director for five years. Wright also served as editor of EE Times' Digital Home and Power Management websites.
Currently, Wright is working as a consultant for a number of technology companies and writing under his own byline for the Intel Embedded Community website and for LEDs Magazine.
Wright has won numerous industry awards, including ASBPE national wards for EDN's 50th Anniversary Issue and a similar award for the EDN Prying Eyes department. Wright is an expert in the area of digital media and the connected home, having covered the wired and wireless service-provider and in-home networks extensively. This expertise extends from processors and ASSPs all the way up through the end application. Wright graduated from Auburn University in 1978 with a BSEE and a curriculum emphasis on digital design and development with early microprocessors.
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