SY898533L Fanout Buffer

Click to Enlarge - SY898533L Diagram

Precision Differential 3.3V Low Skew LVPECL 1:4 Fanout Buffer
Available at Digi-Key

Micrel, Inc.'s SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK pair while LVPECL, CML, or SSTL input levels can be applied to the PCLK, /PCLK pair. To eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin, the clock enable is synchronized with the input signal.

  Features   Applications
  • Provides four differential 3.3V LVPECL copies
  • Selects between differential CLK, /CLK or LVPECL clock inputs
  • CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL input levels
  • PCLK, /PCLK pair accepts LVPECL, CML, SSTL input levels
  • Guaranteed AC performance over temperature and supply voltage:
         650MHz Maximum output frequency
          < 1.4ns Propagation delay (In-to-Q)
          < 30ps Output skew
          < 150ps Part-to-part skew
         Additive phase jitter, RMS: 0.06ps (typical)
  • 3.3V ±5% supply voltage
  • 0°C to 70°C temperature operating range
  • Available in a 20-pin TSSOP package
  • SONET clock distribution
  • Backplane distribution

         SY898533L Datasheet

RoHS Compliant

Part Number
Part Number
Input Output Frequency
SY898533LKZ 576-3560-5-ND CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL LVPECL 650MHz 3.135V ~ 3.465V 20-TSSOP