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31243 Views 15 Replies Latest reply: Feb 4, 2013 9:26 AM by MikeWeed RSS
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Jan 2, 2013 9:34 PM

LTSPICE run of expected behavior.

Greetings,

I guess you would describe me as a "young player" as a certain Aussie bloke would say.

I have been working on a simple dual complementary MOSFET circuit to act as a bistable high-side power latch.

The trouble stems from the fact that I think LTSPICE has been lying to me about the behaviour of the latch.

 

Here  is an image of the LTSPICE run for the circuit (I have been most  careful about specifiying the correct models, which have been

updated  directly from IRF).  It can be seen that a short on pulse is sufficient  to turn on the high-side P-channel enhancement mode pass transistor,  while a longer pulse is required to turn off the pass transistor.  In the simulation it would appear to be functioning correctly, but when the circuit is constructed the behavior goes all wrong.  When input power is applied the circuit sits for approx. six seconds, then turns on all by itself.  If I then apply the long pulse the circuit turns off the pass element, but two seconds after the control pulse goes low the latch turns on again.  Yuck.

J.R. the newb.

 

 

  • Rick designspecialist-power 63 posts since
    Mar 22, 2011
    Currently Being Moderated
    Jan 7, 2013 8:44 AM (in response to Mister_Widget)
    LTSPICE run of expected behavior.

    The image posted doesn't show up terribly well--all I'm seeing is the menu bar of your program...  If you could post a schematic as well as your simulation results, it would be helpful.

     

    Generally speaking though there are a number of things that can go wrong between simulation and a breadboard; you might have made an error in circuit construction, the SPICE models might not be perfectly accurate on some important point, or your model might not include all of the elements that are present in your actual circuit-things like trace impedances, leakage resistances across the PCB, coupling to the outside world (60 Hz fields are everywhere...) etc. 

     

    If you've got a 'scope, I'd suggest watching what happens at the various critical nodes in your real-life circuit, looking for behaviors that aren't what you were expecting.  Bear in mind as you do so that the 'scope probe does present a finite impedance to ground, which has the potential to "fix" or otherwise alter the observed phenomenon by its presence.  It seems like the time scale of the problem is slow enough though that you may be able to find some clues using a multimeter also, if a 'scope isn't available.

     

    Finally (to paraphrase one of the famous figures in the field) the most reliable simulation engine available is PbSnSPICE version 63.37

      • Rick designspecialist-power 63 posts since
        Mar 22, 2011
        Currently Being Moderated
        Jan 21, 2013 12:24 PM (in response to Mister_Widget)
        Followup - original and DUT.

        In your first post you mentioned that the circuit turns on ~6 seconds after power up, though above you mentioned that the false turn-on on power up occurs "immediately" which is a rather different thing; "immediately" would suggest some sort of dynamic problem, possibly relating to dV/dt-induced turn on of the FETs, whereas "after 6 seconds" would suggest more of a steady-state problem, such as unanticipated current flows that aren't getting included in your SPICE model.

         

        Setting aside the obvious macro-scale variation in general function, what discrepancies are there between your simulated and physical waveforms, at a node-by node level?  That info should give you a clue as to where the problem lies.  Often as not in a prototype circuit, it's a construction/assembly error; a rogue solder blob, an pin/pad assignment error in your CAD package, etc. 

         

        The complementary FET approach has some merits in terms of flexibility in application voltage range; add a few zeners across gate & source to limit the applied voltage and you could extend the application voltage range closer to the Vds limits of the FETs, rather than the Vgs limits.  That design approach does have some potential skittishness as you're currently discovering however.

         

        That said, there's little to say you couldn't combine the bi-stable element of your first circuit with the compelmentary switch arrangement of the second.  Assymetric switching times could be achieved using diodes and different resistor values to change the time constant based on direction of current flow.  Of course, you could also use a cheap microcontroller (such as a PIC10F200T-I/OTCT-ND or ATTINY5-TSHRCT-ND) as your bistable element, in order to have arbitrarily programmable switching times for a similar cost as the dual inverter in your schematic.

  • MikeWeed Novice 62 posts since
    Oct 21, 2011
    Currently Being Moderated
    Jan 22, 2013 1:57 PM (in response to Mister_Widget)
    Followup - original and DUT.

    "High" technology (such as SPICE) is no substitute for intelligent use of wetware. One problem with the second circuit is that the output load can affect the control via the nmos FET. The first circuit was much better in this regard.

    You want to turn on the p FET when the switch is pressed for a short time, and turn it off when pressed for a longer time. I recommend a circuit like the attached that uses a CD4013 dual flip-flop that can operate on a supply

    voltage up to 18v. You did not say what voltage you are trying to switch, but in case it is more than 18v I included a zener diode to limit the CD4013 supply.

    The principle of the attached circuit is that a short press takes pin 8 high while pin 10 is low, thereby taking pin 13 high and turning on the n FET, and thus the p FET. If the switch is held down longer, the + pulse on pin 8 disapears and pin 10 rises above the threshold, which turns off the n FET. I used the other half of the CD4013 as a power-on-reset circuit where the rising input voltage produces a pulse on pin 1 that keeps pin 13 low for a time. Thereafter, the first section performs no function until the power is turned on again.

      • MikeWeed Novice 62 posts since
        Oct 21, 2011
        Currently Being Moderated
        Jan 23, 2013 8:27 AM (in response to Mister_Widget)
        Followup - original and DUT.

        Resending image ... darn newfangled devices!powersw 002.jpg

            • MikeWeed Novice 62 posts since
              Oct 21, 2011
              Currently Being Moderated
              Jan 24, 2013 3:19 PM (in response to Mister_Widget)
              Followup - original and DUT.

              You will need to keep D1 with a zener voltage of whatever the logic chip needs, but with a max of 12v you can dispense with D2 and R3 in my diagram, since the irf7343 can handle up to 20v gate to source. Looking over my diagram again, I see I should have the D3 cathode tied directly to pin 10 on the CD4013 as shown, but there should be another resistor, say 10k, between pin 10 and the junction of R5 and R7. This will prevent the POR pulse from being shorted out by the large capacitor C4.

              The IRF7343 specs show the n FET can be turned on at a rather low voltage, which reduces the constraints on the logic supply voltage. You could probably get by with 3.3v logic. Many logic families have dual flip-flops; if you go to a different type (to get a smaller package), be aware that something like a 74hc74 has Set and Reset polarities opposite from that of the CD4013, so you will need to swap these pins from what I show in my diagram. Good luck!

                • MikeWeed Novice 62 posts since
                  Oct 21, 2011
                  Currently Being Moderated
                  Jan 30, 2013 9:57 AM (in response to Mister_Widget)
                  Re: Followup - original and DUT.

                  Almost right, but the POR diode should go directly to the second latch Reset input. Also, the zener diode voltage should be chosen for the operating voltage of the logic chip. It occurs to me that, since the Clock and D inputs are not being used, you can make the 2 set-reset latches from cross-coupled NOR gates. Then, if the NOR gates have Schmitt trigger inputs, you can alleviate a possible problem due to switch bounce. If you do not have hysteresis on the inputs, opening the switch immediately after the p FET is turned off could cause a pulse to be sent to the 2nd latch Set input if the switch bounces. This will turn the circuit back on immediately. But with Schmitt trigger inputs, the Reset input will be held above the turn-off threshold for a time after the switch is released, and if this time is longer than the switch bounce time, the latch will remain in the reset state. This means that the circuit cannot be turned on immediately after being turned off, but this may be a good thing. I am sending a circuit using cross-coupled NOR gates with hysteresis, and using a 5.1V Zener diode for logic power. This is becoming an elegant little circuit...powersw 003.jpg

                    • MikeWeed Novice 62 posts since
                      Oct 21, 2011
                      Currently Being Moderated
                      Feb 4, 2013 9:26 AM (in response to Mister_Widget)
                      Re: Followup - original and DUT.

                      Putting the LED and its series resistor between the 5.1v reference and the n FET drain is OK, if you don't mind the fact that the LED indicates that the p FET is getting a turn-on signal, not that there is actually voltage on the output. So if the output is shorted to ground, or the p FET is burned out, the LED will still light. A typical LED has about 1.2v voltage drop, leaving 3.9V across the resistor, so for a typical LED current of 10ma the resistor should be 390 ohms.

                      You could put another LED and series resistor across the 5.1V Zener diode to indicate that power is available at the input.

                      I'm not sure what you mean by bipolar load. If you mean that you want to pass a negative input voltage to the output, the present circuit will not work. Not only do you not get the 5.1V to supply the logic, but the output FET drive voltage is wrong. For an enhancement mode  p FET, the gate voltage must be sufficiently more negative than the source to turn on.

                      As for Zener diode protection on the FET gate, most FETs will withstand 20V (some even 30V) of either polarity between the gate and source. If this limit may be exceeded, you will need a Zener diode between gate and source and a resistor in series with the gate to limit the Zener diode current.

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