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1594 Views 0 Replies Latest reply: Aug 26, 2014 11:32 PM by Riley RSS
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Aug 26, 2014 11:32 PM

Question on Flipflop Initial State and Output

In the picture attached, it's described that when the clock goes from low to high, with a constant data at low, the output Q will be 0. Also, when the clock is at high, no changes at the input can change the output. Why does the output lock? and if so, where is this type of device used?



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