|The Swissbit DIMM module provides a highly-ruggedized, 240-pin, 72 bit DDR3 SDRAM ECC Small Outline module which is organized as 256 M x 72 high speed CMOS memory arrays. Enhanced ruggedness is obtained through the use of a high-performance, 240-pin socket connector system and the use of standoffs with screw attachment, firmly holding the CPU and memory module together. The module uses internally-configured octal-bank DDR3 SDRAM devices, and achieves high-speed operation by using double data rate architecture. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto pre-charge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access.
The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation, providing a high effective bandwidth. A self-refresh mode is provided and a power-saving "power-down" mode. All inputs, and all full drive-strength outputs, are SSTL_15 compatible. The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM using the standard I2C protocol. This non-volatile storage device contains 256 bytes. The first 128 bytes are utilized by the XR-DIMM manufacturer (Swissbit) to identify the module type, the module’s organization, and several timing parameters. The second 128 bytes are available to the end user.