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72-Bit DDR3 SDRAM Module

Swissbit's 204-pin, 72-bit DDR3 small outline, dual-in-line double data rate synchronous DRAM module


Swissbit's 72-Bit DDR3 SDRAM ModuleSwissbit's recent DRAM module is an industry standard 204-pin, 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line Memory Module (SO-UDIMM) which is organized as x72 high-speed CMOS memory arrays. The module uses internally configured octal-bank DDR3 SDRAM devices, and uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation to provide a high effective bandwidth. A self-refresh mode is provided and a power-saving “powerdown” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible.

The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM using the standard I2C protocol. This nonvolatile storage device contains 256 bytes, with the first 128 bytes utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several timing parameters. The second 128 bytes are available to the end user.

Features
  • Module organization: dual rank 1024M x 72
  • 1.5 V I/O ( SSTL_15 compatible)
  • Fly-by-bus with termination for C/A & CLK bus
  • On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM
  • Gold-contact pad
  • This module is fully pin and functional compatible to the JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM design spec. and JEDEC- Standard MO-268.
  • Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type.
  • 512 Mx8 DDR3 SDRAM in PG-TFBGA-78 package
  • VDD = 1.5 V ±0.075 V, VDDQ 1.5 V ±0.075 V
  • The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)]
  • DDR3 - SDRAM component Samsung K4B4G0846B
  • 8-bit prefetch architecture
  • On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity.
  • Refresh, Self-Refresh and Power Down Modes
  • ZQ Calibration for output driver and ODT
  • System Level Timing Calibration Support via Write Leveling and Multi-Purpose Register (MPR) Read Pattern

Digi-Key P/N Manufacturer P/N Description  
1052-1066-ND SGN08G72G1BB2SA-CCWRT SDRAM DDR3 8GB 204 SO-UDIMM Datasheet