SN74AUP2G125 Low Power Dual Bus Buffer Gate

Low-power dual bus buffer gate with 3-state outputs

SN74AUP2G125 Low Power Dual Bus Buffer GateThe AUP family is TI's premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity.

The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V VCC operation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, output-enable should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Features Benefits
  • Available in the Texas Instruments NanoFree™ package
  • Low static-power consumption
    (ICC = 0.9 µA max)
  • Low dynamic-power consumption
    (Cpd = 4 pF typ at 3.3 V)
  • Low input capacitance (CI = 1.5 pF Typ)
  • Low noise – overshoot and undershoot
    <10% of VCC
  • Input-disable feature allows floating input conditions
  • Ioff supports partial-power-down mode operation
  • Input hysteresis allows slow input transition and better switching noise Immunity at input
  • Wide operating VCC range of 0.8 V to 3.6 V
  • Optimized for 3.3-V operation
  • 3.6-V I/O tolerant to support mixed-mode signal operation
  • tpd = 4.6 ns max at 3.3 V
  • Suitable for point-to-point Applications
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD performance tested per JESD 22
    • 2000-V human-body model (A114-B, class II)
    • 200-V machine model (A115-A)
    • 1000-V charged-device model (C101)
    • Extends battery life for portable applications
    • Can interface with next generation processors
    • Lowest-power family
    • Excellent signal integrity and low noise
    • WCSP is 70% smaller than SC-70, which makes it ideal for space constrained PCBs

    Applications

    • PDAs
    • Cell phones
    • Notebook and Sub-notebook PCs

    Diagram

    SN74AUP2G125

    ImageManufacturer Part NumberDescriptionLogic TypeNumber of ElementsAvailable Quantity
    SN74AUP2G125YFPR datasheet linkIC BUS BUFF TRI-ST DL 8DSBGASN74AUP2G125YFPRIC BUS BUFF TRI-ST DL 8DSBGABuffer, Non-Inverting21712 - Immediate
    SN74AUP2G125YFPR product page link
    Published: 2008-12-23