NXP Semiconductor's DSP56303 is intended for use in telecommunication applications such as multi-line voice/data/fax processing, video conferencing, audio applications, control, and general digital signal processing.
The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high performance, single clock cycle per instruction engine. While retaining code compatibility it provides a twofold performance increase over NXP's popular DSP56000 core family.
Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0 - 3.6 volts. The DSP56300 core family offers a high level of performance in speed and power provided by its rich instruction set and low power dissipation for wireless, telecommunications, and multimedia products.
- 100 million multiply-accumulates per second (MMACS) with a 100MHz clock
- Object code compatible with the DSP56000 core
- Highly parallel instruction set
- Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)
- 56-bit parallel barrel shifter
- 24-bit or 16-bit arithmetic support under software control
- Position-independent code support
- Addressing modes optimized for DSP applications
- On-chip memory-expandable hardware stack
- Nested hardware DO loops
- Fast auto-return interrupts
- On-chip concurrent six-channel DMA controller
- On-chip phase-lock loop (PLL) and clock generator
- On-chip emulation (OnCE) module
- JTAG test access port (TAP)
- On-chip instruction cache controllerAddress tracing mode reflects internal accesses at the external port