Analog Devices' AD9683 is a 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9683 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined architecture with integrated output error-correction logic. The ADC core features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty-cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The JESD204B high-speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.
The ADC output data is routed directly to the JESD204B serial-output lane. These outputs are at CML voltage levels. Data can be sent through the lane at the maximum sampling rate of 250 MSPS, which results in a lane rate of 5 Gbps. Synchronization inputs (SYNCINB± and SYSREF±) are provided.
Flexible power-down options allow significant power savings when desired. Programmable overrange level detection is supported via the dedicated fast-detect pins.
- Diversity radio systems
- Multimode digital receivers (3G)
- TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse-path receivers
- Smart antenna systems
- Electronic test and measurement equipment
- Radar receivers
- COMSEC radio architectures
- IED detection/jamming systems
- General-purpose software radios
- Broadband data applications
- Ultrasound equipment