Altera's Cyclone V FPGAs provide the market's lowest-system-cost and lowest-power-FPGA solution for applications in the industrial, wireless, wireline, broadcast, and consumer markets. The family integrates an abundance of hard-intellectual property (IP) blocks to enable you to do more with less-overall system cost and design time. The SoC FPGAs in the Cyclone V family offer unique innovations such as a hard-processor system (HPS) centered around the dual-core ARM® Cortex®-A9 MPCore™ processor with a rich-set of hard-peripherals to reduce system-power, cost, and board size.
Because Cyclone V FPGAs integrate an abundance of hard(IP) blocks, you can differentiate and do more with less overall system cost, power, and design time. Key hard-IP blocks include the following:
- Hard-memory controllers supporting 400 MHz DDR3 SDRAM with optional error correction code (ECC) support
- PCI Express® (PCIe®) Gen2 with multifunction support
- Variable-precision digital signal processing (DSP) blocks
- HPS Dual-core ARM Cortex-A9 MPCore processor
The devices are built on TSMC's 28 nm Low-Power (28LP) process, which brings down the power and cost required by cost-sensitive applications.
- Up to 40% lower-total-power compared with Cyclone IV GX FPGAs
- Lowest-power serial transceivers with 88 mW maximum-power consumption per channel at 5 Gbps
- Over 4,000 MIPS (Dhrystones 2.1 benchmark) processing performance for under 1.8 W (for SoC FPGA)
- Lower-power due to increased use of hard-IP-blocks