With the world moving toward ubiquitous wireless connectivity and even fixed-function devices like a cellphone employing several different bands and protocols co-existing in a small space, the job of the wireless designer is not getting easier. Modern smartphones and tablets can be transceiving simultaneously data on 3G/4G, (and soon to be 5G) voice and data, Bluetooth, Wi-Fi, and possibly GPS. The emerging Personal Area Networks supporting “wearable” computers and peripherals will add even more RF responsibility to already communications-heavy designs.
Even within the same frequency bands, different and sometimes non-interoperable protocols and services are fighting for recognition, acceptance, timeslots, and market share. Consider the 2.4 GHz ISM band for example. We have Bluetooth, Wi-Fi, ZigBee, cordless phones, telemetry, and several other services all existing in this space.
It does not stop there. Designers who need to connect to a changing wireless world must be aware of chipset developments, protocol stacks, intellectual property, and a multitude of development environments, certifications, tools, and test equipment.
What if there was another way? What if one single RF section could do it all?
This article will look at the emerging software-defined radio (SDR) architecture and the parts that support it. SDR holds the promise of a single, ultra-flexible RF processing system that can be programmed to operate with multiple frequencies and multiple protocols simultaneously. In addition, the fully programmable and signal-processing nature of the software-defined radio makes it an ideal hedge against new protocols and services that emerge, but might not quickly take hold. All parts, data sheets, tutorials, and development kits referenced here can be found on the Digi-Key website.
You’re being replaced
Radios have fairly compartmentalized functions that work together. A receiver, for example, will use an antenna to access a low-level signal, amplify it, filter it, engage in frequency mixing, demodulate a recovered signal (using one or more of several modulation/demodulation schemes) and present output data as analog or digital waveforms. Transmitters modulate instead of demodulate, but do the same process in reverse.
Highly optimized hardware blocks have evolved to achieve stability, clarity, low drift, good temperature stability, small size, low power, good sensitivity, and easy systems integration. The goal of an SDR, in a sense, is to replace these highly trained workers with programmable and automated technology.
Ideally, an antenna would connect to an A/D converter, which feeds the broadband waveform to a signal-processing stage. The signal-processing block would then extract the desired signal from the desired channel and the desired band at the desired timeslot (if applicable). However, the world is not that simple, at least not yet.
For one thing, GHz speed A/D converters are not available. What’s more, while memory depths have grown exponentially, at 5 GHz bands for example, the memory requirements of the scheme just outlined would take 10 Gbytes to create a one second buffer (assuming 16-bit samples).
On the other hand, several processor and IC advances have certainly made it possible to partition the RF front-end stages into flexible, high-performance processing blocks that do most of the high-frequency, signal-intensive recovery. At that point data is passed to a general-purpose processor, like a PC, tablet, or even smartphone, which in itself can use software to create user interfaces, controls, displays, and even take on some of the modulation/demodulation schemes using A/D and D/A interfaces or sound cards (Figure 1).
Figure 1: Dense and high-speed front-end hardware captures signals directly from the antenna to perform channelization and sample-rate conversion. This can be fed directly into a digital signal processing stage, which performs baseband processing. A general-purpose processor, such as a PC, can use analog inputs in the manner of a sound card to perform demodulation and final-signal inputs/outputs.
Discrete hardware can be replaced with programmable stages for filters, mixers, modulators, demodulators, detectors, comparators, amplifiers, oscillators, and more. Several devices are already available for this and take direct aim at SDR designs. Consider, for instance, the RF Agile Transceiver from Analog Devices
. Designated AD9364
, it combines an RF front-end with a wideband and flexible mixed-signal base-band processor (Figure 2).
Figure 2: The modular 1 x 1 transceiver features 12-bit A/D and D/A stages with parallel-data buses. On-chip local oscillators and mixers are usable from 70 MHz bands up through 6 GHz.
Although it was designed initially for 3G/4G RF data communications, it is configurable via a digital interface to a host processor, which allows it to function as an agile transceiver for many protocols and bands. The inclusion of integrated, high-end frequency synthesizers results in a configurable-digital interface into RF operations.
Frequency range is supported from 70 MHz to 6 GHz, making it useful for legacy as well as modern Wi-Fi band support. This also puts it in the range of GSM, DECT, Bluetooth, Wi-Fi, WiMAX, ZigBee, and many other popular wireless protocols and services.
Other nice features include real-time monitoring and control for signal gains and AGC functions and a 128-tap finite impulse response filter which produces a 12-bit output signal at the appropriate sample rate. The programmability allows its use for both time-division duplex and frequency duplex signaling techniques. It has tunable channel bandwidths (from 200 kHz up to 56 MHz) and can separate out parts of the band for high-data-rate streams, or slice out narrower portions for lower baud signals.
Support is in place as well with the AD-FMCOMMS4-EBZ
development system supporting a full 56 MHz to 6 GHz range.
Another processor companion chip for use in a software-defined radio comes from Lime Microsystems
with its LMS6002DFN
multi-band, multi-standard integrated transceiver chip. This part also features differential input and output RF connect with 12-bit parallel transmit and receive data buses just like the Analog Devices part. The LMS6002DFN covers the 300 MHz to 3.8 GHz bands and also features 12-bit A/D and D/A resolutions and is designed for the emerging femto- and pico-cell base stations and repeaters. This part also uses differential signaling techniques inside for all analog stages. Note how the single part covers WCDMA, HSPA, LTE, GSM, CDMA2000, and IEEE 802.16x radios all under software control.
A particularly nice feature of this part is its dual and separate synthesizers that enable full duplex operation. In addition, two transmitter outputs and three receiver inputs can be active simultaneously. This allows for concurrent support of different protocols and standards.
Another nice feature is its two-stage TX gain control (Figure 3A); one stage in the IF section, the other in the RF section. A single control word controls both I and Q branches. In a similar fashion, there is also three-stage gain control on the input side (Figure 3B). The main LNAs have fine gain control via a 6-bit control word resolving into ±6 dB steps. A 1 dB step on the AGC can reduce gain in preparation for channel filtration.
A Lime Microsystems Product Training Module for the LMS6002
Multi-Function RF Transceiver is available on Digi-Key’s website. In addition, this part is supported via Lime’s MYRIADRF-1
development kit, based on the flexible, multi-standard LMS6002 transceiver and an Altera FPGA module.
Figure 3A: A flexible programmable-gain TX stage takes advantage of two independent programmable-gain amplifiers.
Figure 3B: Three gain-control stages provide flexibility on input-signal conditioning, including the ability to bypass (at 0 dB loss) the low-pass filter.
In addition to parts specifically designed to function within an SDR, high-end general-purpose parts that have a lot of resources, peripherals, and processing power can also be used as host to a software-defined radio. One such example comes from Texas Instruments
with its TMS320DM6446AZWT
high-performance, general-purpose DSP. This is truly a system on a chip as the 361 BGA Digital Media IC houses two cores, a high-end ARM926 clocking in at 297 MHz, and a dedicated TMS320C64x+ DSP core clocking in at 594 MHz.
As part of the company’s DaVinci series
, this part houses video, networking, graphics control, mixed signal, smart card, audio, ATA and Flash interface, USB and DDR memory control, to name a few on its lengthy list of features.
The use of the TMS320C64
fixed-point DSP part of the device allows all the existing filters, modulators, demodulators, and other signal-processing algorithms to run concurrently with the digital side. Internally, the independent DSP has its own memory resources and cache to enhance performance and minimize ARM/DSP interactions. TI has an abundance of design tools, app notes, and training material to help get engineers up to speed with such a sophisticated part. An example is the TMDSEVM642
eval module, which supports the C6000, the DaVinci, and the VelociT1.2 series of processors.
A unified RF communications and control approach can be achieved without the need for a large number of individual devices. While still in the early stages of refinement, there are enough examples of software-defined radios to show the flexibility and capability of this approach, and it is only going to get better. In its purest form, and sometime in the future, an SDR receiver might consist simply of an analog-to-digital convert chip connected to an antenna. All the filtering and signal detection can take place in the digital domain, perhaps in an ordinary personal computer, smartphone, tablet, laptop, or wearable computer.
For more information about the parts discussed in this article, use the links provided to access product information pages on the Digi-Key website.