Building a Software-Defined Radio

By European Editors

Contributed By Publitek Marketing Communications

Software-defined radio (SDR) is a complex combination of RF, data conversion, and digital signal processing. Additionally, these devices now have the performance to build cost-effective SDR systems. This article looks at how to build an SDR system, including recent open-source developments.

Software-defined systems are becoming increasingly common, with wireless systems leading the way. Using a single architecture to handle a wide range of frequencies and increasingly complex protocols reduces cost and size and can reduce the overall power consumption.

However, building a software-defined radio (SDR) has traditionally not been easy. The front-end has to capture as much of the frequency band as possible and be able to down convert it to be captured by analog-to-digital converters (ADCs) so that the RF stream can be processed to extract the relevant digital data. This has required high-performance tuners, high-speed ADCs, and complex digital signal processors (DSPs), and it is only recently that each element has had the level of performance to implement SDR from discrete components as in Figure 1 from Texas Instruments.

This shows the different elements from the high-speed signal capture through the ADCs to the DSP engines that process the data.

A typical SDR architecture

Figure 1: A typical SDR architecture showing the complexity of the design.

In multi-channel systems, hardware-defined radio (HDR) implementations require a significant amount of analog signal processing for every channel, leading to large board area, high analog design complexity, limited flexibility, and susceptibility to RF interference. A gigasample ADC allows multiple narrowband and wideband channels to be combined into a single ultra-wideband channel; thereby pushing channelization from the analog domain into the DSP, FPGA, or ASIC, where frequencies and bandwidths can be controlled digitally, enabling maximum system flexibility and re-configurability.

An SDR approach provides benefits through lower analog complexity with smaller boards and lower power consumption and system cost as multiple channels of hardware are replaced with a single system. It is also less susceptible to RF interference so less shielding is required.

While SDR has already been used in military communications and radar systems, it is increasingly being used in 3G/4G base stations and for wideband microwave backhaul, as well as optical networks and the latest test and measurement equipment. With more integration and lower costs, it is also now viable for consumer multimedia applications.

One company, Lime Microsystems, has taken the RF elements and integrated them into a single chip with an open-source hardware design to stimulate the development of SDR systems.

A single chip for SDR

The LMS6002D from Lime Microsystems is a fully-integrated, multi-band, multi-standard RF transceiver for 3GPP (WCDMA/HSPA, LTE), 3GPP2 (CDMA2000), and 4G LTE applications, as well as for GSM pico BTS. It combines the LNA, PA driver, RX/TX mixers, RX/TX filters, synthesizers, RX gain control, and TX power control with very few external components.

Lime Microsystems LMS6002D

Figure 2: The LMS6002D integrated front-end for SDR.

The top-level architecture of the LMS6002D transceiver is shown in Figure 2. Both transmitter and receiver are implemented as zero IF architectures providing up to 28 MHz modulation bandwidth, making this equivalent to a 14 MHz baseband IQ bandwidth.

On the transmit side, the IQ DAC samples from the baseband processor are provided to the LMS6002D on a 12-bit, multiplexed parallel CMOS input-level bus. Analog IQ signals are generated by on-chip transmit DACs and these are fed to the TXINI and TXINQ inputs. The transmit low-pass filters (TXLPF) remove the images generated by zero hold effect of the DACs and then the IQ signals are amplified and a DC offset is inserted in the IQ path by local-oscillator (LO) leakage DACs in order to cancel the LO leakage. The IQ signals are then mixed with the transmit PLL output to produce a modulated RF signal. This RF signal is then split and amplified by two separate variable gain amplifiers (TXVGA2) and two off-chip outputs are provided as RF output.

The transmitter gain control range of 56 dB is provided by the TXVGA1 IF amplifier with a 31 dB range and the TXVGA2 RF amplifier with a 25 dB range. Both these transmitter amplifiers have a 1 dB gain step control.

The LMS6002D provides an RF loop-back option (see Figure 2), which enables the TX RF signal to be fed back into the baseband for calibration and test purposes. The RF loop-back signal is amplified by an auxiliary PA (AUXPA) in order to increase the dynamic range of the loop.

On the receive side, three separate inputs are provided each with a dedicated LNA. The preconditioned RF signal for each port is first amplified by a programmable low-noise amplifier (RXLNA). The RF signal is then mixed with the receive PLL output to directly down convert to baseband. Large AGC steps can be implemented by an IF amplifier (RXVGA1) prior to the programmable bandwidth low-pass channel select filters (RXLPF). The received IQ signal is further amplified by a programmable gain amplifier RXVGA2. DC offset is applied at the input of RXVGA2 to prevent saturation and to preserve receiving in the ADC(s) dynamic range. The resulting analog receive IQ signals are converted into the digital domain using the on-chip receive ADCs and provided as an output to the baseband processor on a multiplexed 12-bit CMOS output level parallel bus. The receive clock, RX_CLK, is provided off-chip at the RX_CLK_OUT pin and can be used to synchronize with the baseband digital receive data sampling clock.

By closing the RXOUT switch and powering down RXVGA2, the RXOUTI and RXOUTQ pins can be used as IQ ADCs inputs. In this configuration, the ADCs can be used to measure two external signals, such as an off-chip PA temperature sensor or peak detector.

Two transmitter outputs (TXOUT1, TXOUT2) and three receiver inputs (RXIN1, RXIN2, RXIN3) are provided for multi-band operation. The receiver has three gain control elements, RXLNA, RXVGA1, and RXVGA2. The RXLNA gain control consists of a single 6 dB step for AGC when large in co-channel blockers are present and a reduction in system NF is acceptable. The main LNAs (LNA1 and LNA2) have fine gain control via a 6-bit word which offers ±6 dB control intended for frequency correction when large input bandwidths are required.

The RXVGA1 block provides 25 dB of control range, a 7-bit control word is used and the response is not log-linear. The maximum step size is 1 dB as the RXVGA1 is intended for AGC steps needed to reduce system gain prior to the channel filters when large in-band blockers are present. This gain can be under control of the baseband or fixed on calibration. Meanwhile, RXVGA2 provides the bulk of gain control for AGC if a constant RX signal level at the ADC input is required. It has 30 dB gain range control in 3 dB steps.

In order to enable full duplex operation, the LMS6002D contains two separate synthesizers (TXPLL, RXPLL) both driven from the same reference clock source PLLCLK. The PLLCLK signal is provided at the PLLCLKOUT output pin and can be used as the baseband clock.

The transmitter output ports are optimized for a 65 Ω differential load, the final-stage amplifiers are open drain and require +3.3 V voltage supply. However, the receiver inputs are all different. RXIN1 is the low-frequency input and can operate in the range 0.3 – 2.8 GHz, RXIN2 is the high-frequency input and can operate in the range 1.5 – 3.8 GHz. Both RXIN1 and RXIN2 require matching circuits for optimum performance while RXIN3 is a broadband input covering the range 0.3 – 3.0 GHz with a 200 Ω differential input that is typically matched with a wideband transformer.

Differential signaling is done in the receive and transmit analog paths throughout the chip using two low-phase noise synthesizers to enable full duplex operation. Both synthesizers are capable of output frequencies up to 3.8 GHz. Each synthesizer uses a fractional-N PLL architecture and the same reference frequency is used for both synthesizers and is flexible between 23 to 41 MHz. The synthesizers produce a complex output with a suitable level to drive IQ mixers in both the TX and the RX paths.

The LMS6002D can accept clipped sine as well as the CMOS level signals as the PLL reference clock. Both DC and AC coupling are supported, but internal buffer self-biasing must be enabled for the AC coupling mode. PLL reference clock input can also be low-voltage CMOS (2.5 V or 1.8 V, for example) which is implemented by lowering the clock buffer supply.

The device integrates highly-selective low-pass filters in both TX and RX paths and the filters have a programmable pass band in order to provide more flexibility on the DAC/ADC clock frequency and also to provide excellent adjacent channel rejection in the receive chain. The filters are also tunable to compensate for process/temperature variation. The TX and RX filters are the same but controlled via SPI link independently.

A key element of the design is that all the functionality of the LMS6002D is fully controlled by a set of internal registers, which can be accessed through a serial port. This allows the controller to set the different criteria for the chip depending on the environment. These are highlighted on the open-source MyriadRF hardware board in Figure 3.

Lime Microsystems LMS6002D SDR front-end

Figure 3: The open-source MyriadRF hardware board for the LMS6002D SDR front-end.

At the front end, new RF-sampling architectures are helping to make SDR more efficient. Texas Instruments has expanded their gigasample-per-second (GSPS) ADC portfolio with a direct RF-sampling family. These RF-sampling ADCs offer performance beyond 2.7 GHz, building on TI’s existing 12-bit ADC family. Together with its wideband amplifiers and low-noise clock and timing solutions, this enables new RF-sampling and wideband SDR systems that efficiently increase system capacity, scalability, and flexibility while simultaneously reducing system size, weight, power, cost, and design time.

Benefits of RF-Sampling

RF-sampling ADCs can solve some of the challenges of integration. A single direct RF-sampling ADC can replace an entire IF- or ZIF-sampling subsystem of mixers, LO synthesizers, amplifiers, filters, and ADCs, while reducing bill of materials (BOM) cost, design time, board size, weight, and power.

In addition, the analog frequency down-conversion function is moved into the DSP, FPGA, or ASIC, where frequencies and bandwidths can be controlled digitally, enabling maximum system flexibility and re-configurability. The 1.8 GHz Nyquist bandwidth of the RF-sampling ADC family ensures the solution can scale up easily for wider bandwidths in future products.

A single direct RF-sampling ADC can replace an entire IF- or ZIF-sampling subsystem, with the filters and mixers implemented in digital, enabling greatly increased system programmability and scalability. These are pin-compatible from 500 MSPS to 3.6 GSPS which reduces design time and cost and makes future upgrades easy.

These are included on the small form-factor Development Platform. This uses the TMS320DM6446 DSP system-on-chip with a 594 MHz TMS320C64x+ DSP core alongside a 297 MHz ARM926 processor core and a rich set of peripherals including serial ports, USB, EMAC, DDR2 EMIF, as well as video ports. A Virtex-4 SX35 FPGA from Xilinx provides additional hardware processing. The ADS5500, 125 MSPS, 14-bit dual-channel ADC sits alongside the 500 MSPS, 16-bit dual-channel DAC5687, and the board allows 5 MHz or 20 MHz channels to be selected. Additional boards can be stacked onto the development platform, with an RF module operating between 360 MHz and 960 MHz, as well as an optional second RF module for full-duplex operation or to cover additional bands.

A high-performance front-end for SDR

When working with high-performance data converters, a high-performance broadband modulator is essential. The ADL5375 from Analog Devices is a broadband quadrature modulator designed for operation from 400 MHz to 6 GHz. The phase accuracy and amplitude balance enable high-performance intermediate frequency or direct radio frequency modulation for SDR communication systems.

Analog Devices ADL5375 broadband quadrature modulator

Figure 4: The ADL5375 broadband quadrature modulator.

The silicon germanium bipolar architecture (Figure 4) provides a broad baseband bandwidth along with an output-gain flatness that varies no more than 1 dB from 450 MHz to 3.5 GHz. These features, coupled with a broad band output return loss of ≤−12 dB, make the ADL5375 ideally suited for broadband zero IF or low IF-to-RF applications, broadband digital predistortion transmitters, and multiband radio designs. It accepts two differential baseband inputs and a single-ended LO and generates a single-ended 50 Ω output. The two versions offer input baseband bias levels of 500 mV (ADL5375-05) and 1500 mV (ADL5375-15).

The ADL5375 can be divided into five circuit blocks: the LO interface, baseband voltage-to-current (V-to-I) converter, mixers, differential-to-single-ended (D-to-S) stage, and the bias circuit as in Figure 5.

Analog Devices ADL5375 modulator diagram

Figure 5: The ADL5375 modulator can be broken down into five separate blocks.

The LO interface generates two LO signals in quadrature. These signals are used to drive the mixers. The I/Q baseband input signals are converted to currents by the V-to-I stages, which then drive the two mixers. The outputs of these mixers combine to feed the output balun, which provides a single-ended output. The bias cell generates reference currents for the V-to-I stage.

The LO interface consists of a polyphase quadrature splitter that sets the input impedance and a limiting amplifier. Each quadrature LO signal then passes through a limiting amplifier that provides the mixer with a limited drive signal.

The LO input can be driven single-ended or differentially. For applications above 3 GHz, improved OIP2 and LO leakage may result from driving the LO input differentially.

The differential baseband inputs (QBBP, QBBN, IBBN, and IBBP) present high impedance. The voltages applied to these pins drive the V-to-I stage that converts baseband voltages into currents. The differential output currents of the V-to-I stages feed each of their respective mixers. The DC common-mode voltage at the baseband inputs sets the currents in the two mixer cores and varying the baseband common-mode voltage influences the current in the mixer and affects overall modulator performance. The recommended DC voltage for the baseband common-mode voltage is 500 mVDC for the ADL5375-05 and 1500 mV for the ADL5375-15.

The ADL5375 has two double-balanced mixers: one for the in-phase channel (I channel) and one for the quadrature channel (Q-channel). The output currents from the two mixers sum together into an internal load. The signal developed across this load is used to drive the D-to-S stage, which consists of an on-chip active balun that converts the differential signal to a single-ended signal. The balun presents 50 Ω impedance to the output so that no matching network is needed at the RF output for optimal power transfer in a 50 Ω environment.

The I/Q modulator is designed to interface easily to the AD9779A high-speed DAC, as they are well-matched devices with the same bias levels and similar high signal-to-noise ratios (SNR). The matched bias levels of 500 mV allow for a glueless interface, there is no requirement for a level-shifting network that would add noise and insertion loss along with extra components. The addition of the swing-limiting resistors (RSLI, RSLQ) allows the DAC swing to be scaled appropriately without loss of resolution or of the 0.5 V bias level. The high SNR of each device preserves a high SNR through the circuit.

The ADL5375 is designed to interface with minimal components to members of the Analog Devices family of TxDAC converters (AD97xx) to easily build an SDR system. The baseband inputs of the ADL5375 require a DC common-mode bias voltage of 500 mV, and with each AD9779A output swinging from 0 mA to 20 mA, a single 50 Ω resistor to ground from each of the DAC outputs provides the desired 500 mVDC bias. With just the four 50 Ω resistors in place, the voltage swing on each pin is 1 VPP. This results in a differential voltage swing of 2 VPP on each input pair.

By adding resistors RSLI and RSLQ to the interface, the output swing of the DAC can be reduced without any loss of DAC resolution. The resistor is placed as a shunt between each side of the differential pair. This has the effect of reducing the AC swing without changing the DC bias already established by the 50 Ω resistors.

It is generally necessary to low-pass filter the DAC outputs to remove image frequencies when driving a modulator. The above interface lends itself well to the introduction of such a filter. The filter can be inserted between the DC bias setting resistors and the AC swing-limiting resistor. Doing so establishes the input and output impedances for the filter.


Building a software-defined wireless system is becoming easier with the high performance and highly-integrated parts now available. The receive, transmit, and modulation stages are now integrated into a flexible single chip that can be controlled by an external microcontroller, or higher-performance parts can be gluelessly combined on development boards to speed up the design process.
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