The popularity of DC/DC switching voltage converters primarily derives from their efficient regulation over a wide range of voltage inputs and output current compared with linear regulators. However, at lower loads, efficiency tails off as the quiescent current of the converter IC itself becomes the significant contributor to system losses.
Leading power component manufacturers now offer a range of “dual-mode” switching converters that automatically shift from the popular pulse width modulation (PWM) regulation method to a pulse frequency modulation (PFM) technique at a preset current threshold in order to improve efficiency under low loads.
This article describes how PFM works, explains its benefits and some of its disadvantages, and then considers how some silicon vendors implement the technique in their integrated power chips.
PWM vs. PFM
PWM is not the only technique for regulating the output of a switching converter. Instead of modifying the duty cycle of a fixed-frequency square wave to regulate the output of a power supply, it is also possible to use a constant duty cycle and then modulate the square wave’s frequency (PFM) to achieve regulation. DC/DC voltage converters equipped with constant-on-time or constant-off-time control are typical examples of PFM architecture.
A second example of a PFM architecture is a so-called hysteretic voltage converter that uses a simple method for regulation whereby the MOSFET is turned on and off based on the output-voltage changes sensed by the converter. This architecture is sometimes referred to as a “ripple regulator” or “bang-bang controller” because it continuously shuttles the output voltage back and forth to just above or below the set point. Hysteresis is used to maintain predictable operation and to avoid switch chatter. Because the hysteretic architecture varies the drive signal to the MOSFETs based on the operating conditions of the circuit, the switching frequency varies.
PFM architectures do offer some advantages for DC/DC conversion, including better low-power conversion efficiency, lower total solution cost, and simple converter topologies that do not require control-loop-compensation networks, but are less popular than PWM devices due to some notable drawbacks.
The first is the control of EMI. Filtering circuits for a fixed-frequency switching converter are much easier to design than those for a device that operates across a wide range of frequencies. Second, PFM architectures tend to lead to greater voltage ripple at the output that can cause problems for the sensitive silicon being supplied. Third, PFM operation at low (or even zero) frequency increases the transient response time of the switching converter that could lead to slow response and consumer disappointment in some portable applications.
However, by combining the merits of a PWM architecture with those of a PFM device in a monolithic “dual-mode” switching converter, manufacturers can offer a solution with high efficiency across its entire operating range. The EMI concerns associated with PFM are mitigated to a great extent because the root cause of such interference is fast switching at high currents and high voltages, whereas in dual-mode chips, variable-frequency operation is only used during low-current and low-voltage operation.
Energy losses in a switching voltage regulator
The most common technique for regulating the voltage of a switching device is to use an oscillator and PWM controller to produce a rectangular pulse wave that toggles the unit’s internal MOSFET (or MOSFETs in a synchronous device) at a set frequency typically in the hundreds of megahertz range. (Higher frequencies allow smaller magnetic components at the expense of greater electromagnetic interference [EMI] challenges.) The output voltage of the regulator is proportional to the duty cycle of the PWM waveform.
Generally the technique works well, but at low loads efficiency is compromised. To understand why, it pays to consider where losses, energy drawn at the voltage regulator’s input that is not transferred to the output load, occur.
There are four main sources of loss in a switching regulator. The first is the dynamic loss due to the energy used to charge and discharge the MOSFET gate capacitance, and is highest when the transistor(s) operate at high frequency. These switching losses occur when current flows through the drain-source channel while there is significant differential voltage across it. Other MOSFET losses occur when passing high currents through the nonzero channel resistance of the power-switching elements. (This is why power component manufacturers work so hard to reduce the “on-resistance” of their products.)
In addition to the switching components, the passive devices in the switching regulator’s circuitry are also prone to inefficiencies. For the inductor, the losses result from conduction (in the windings) and magnetic core. For capacitors, the losses are typically associated with the equivalent series resistance (ESR) of the component and are determined by the capacitance of the device, its operating frequency, and its load current.
There are two ways to implement a switching regulator. An engineer can either construct a device from scratch using discrete components or they can base the power supply on one of many converter ICs available from major semiconductor vendors such as Texas Instruments
, Linear Technology
, and Fairchild Semiconductor
. The advantage of a module is that the design process is simplified. (See the TechZone article “DC/DC Voltage Regulators: How to Choose Between Discrete and Modular Design
However, the converter IC itself contributes to the overall loss of the switching regulator. For example, some energy is needed to provide internal bias currents for amplifiers, comparators, and references, but the dominant losses for the IC are associated with the internal oscillator and drive circuits for the PWM controller. Such losses are relatively insignificant when the switching regulator is subject to high load, but as the load decreases, the losses associated with switching and external passive devices decrease while those associated with the converter IC remain constant.
That presents something of a dilemma for the designer of a portable product. The engineer is under pressure to manage the battery budget, so the choice of an efficient switching regulator (compared to, for example, a linear regulator) seems the obvious choice. (See the TechZone article “Design Techniques for Extending Li-Ion Battery Life
.”) However, portable products spend considerable periods under low-power “standby” or “sleep” modes, where the demand on the switching converter is modest and it is operating relatively inefficiently.
A typical handheld device may draw around an amp when fully operational but demand less than one milliamp when in standby or sleep mode. Considering that the converter IC itself can consume up to a few milliamps simply to preserve its operational status, it is little surprise that the conversion efficiency is poor under low-load conditions because the regulator’s quiescent current represents a significant fraction of the total load.
To address the dominant losses (that is, those associated with the internal oscillator and drive circuits for the PWM controller) a designer can select one of many dual-mode switching converters on the market. The devices combine normal PWM operation with a PFM technique (that typically features variable frequencies typically much lower than the normal fixed frequency when operating under PWM).
When a dual-mode switching converter operates at moderate to high currents, it runs in continuous-conduction mode (whereby the current in the inductor never falls to zero). As the load current decreases, the converter may switch to discontinuous mode (when the current in the inductor does fall to zero due to the light load). At very light loads, the converter goes into PFM (sometimes referred to as “Power Saving Mode” [PSM] by manufacturers). Other vendors take variable-frequency operation to an extreme by stopping the oscillator altogether (often referred to as “pulse skipping”).
It should be noted that the use of PFM at low loads does not mean the switching converter uses a PFM architecture, rather, it employs an PWM architecture that is able to utilize PFM operation as required.
Under light-load conditions, a switching converter’s output capacitor can maintain the output voltage for some period of time between switching pulses. In the ideal case, the oscillator could be turned completely off at a no-load condition and the output voltage would remain constant due to the charged state of the output capacitor. However, parasitic losses drain the capacitor and the circuit requires at least occasional pulsing of the power switches to maintain the regulated output voltage in regulation.
During PFM operation the output power is proportional to the average frequency of the pulse train, and the converter operates when the output voltage drops below the set output voltage as measured by the feedback control loop. The frequency of converter switching is then increased until the output voltage reaches a typical value between the set output voltage and 0.8 to 1.5 percent above the set output voltage (Figure 1 illustrates the technique).
Figure 1: PFM varies the frequency of a rectangular pulse train of fixed duty cycle to meet load demand.
Side effects of PFM operation
An increase in voltage output ripple is often observed when the switching converter flips to PFM mode because of the need for a tolerance band (rather than a fixed point) to sense when the power switches need to be turned on again. If a narrower tolerance band is used, the converter switches more frequently, which reduces the power saving. The engineer must decide on the best trade-off between improved low-load efficiency and increased voltage output ripple. Figures 2a and 2b illustrate the difference in voltage ripple for a switching converter operating in PWM and PFM modes, respectively.
Figure 2: Voltage ripple for PWM mode (a) and PFM operation (b) (Courtesy of Analog Devices).
During load transients, any switching converter will exhibit some amount of overshoot during a high-to-low-load transient or undershoot during a low-to-high-load transient. In the case of a converter that is operating in a PSM, the load level is already low, so the next transient will be from low-to-high current (which typically corresponds to transitioning from sleep to active mode). The increased load on the regulator output often results in “output-voltage sag” until the converter loop has time to respond.
Some switching converters include provision to minimize this voltage sag. TI’s TPS62400
employs “dynamic voltage positioning”. During PSM operation, the output-voltage set point is increased slightly (for example, by 1 percent) to anticipate the instantaneous voltage-sagging transient that occurs when the load is suddenly stepped higher. This prevents the output voltage from falling below its desired window of regulation during the initial load transient.
Some devices also offer an enhancement that can be used to balance the compromise between good transient response (best in PWM mode) and low power consumption (best in PSM). The enhancement is an intermediate mode that the engineer can implement using I²C commands to the converter IC that offers better transient response than PSM, but is more efficient than PWM. The intermediate mode is a good option for a system that goes from a high load to a very light load (for example, sleep mode).
PFM in commercial chips
PFM operation at low loads can reduce the quiescent current of the IC from several mA down to a few μA. Figure 3 shows the power-conversion efficiency of the TPS62400 switching converter when it is operating in PWM mode compared to PSM at light-load levels.
Figure 3: Efficiency improvements when implementing PSM for TI TPS62400.
From Figure 3 it can be seen that while PWM mode maintains good efficiency above 100 mA, the use of PSM boosts efficiency to between 80 and 90 percent even at load currents below 1 mA. If the converter operated in PWM mode during such light loads, its operating current would be significantly higher than the load current, resulting in very-poor conversion efficiency (well under 30 percent).
offers several switching converters with PSM. When this mode is entered, an offset induced in the PWM regulation level causes the output voltage to rise, until it reaches approximately 1.5 percent above the PWM regulation level, at which point PWM operation turns off: both power switches are off, and idle mode is entered. The output capacitor is allowed to discharge until VOUT
falls to the PWM regulation voltage. The device then drives the inductor, causing VOUT
to again rise to the upper threshold. This process is repeated as long as the load current is below the PSM current threshold.
The company’s ADP2108
voltage regulator employs PSM to improve efficiency from 40 to 75 percent with an input voltage of 2.3 V and an output current of 10 mA. The chip is a 3 MHz step-down (‘buck’) converter offering 3.3 V output from 2.3 to 5.5 V input at up to 600 mA. Figure 4 shows the point at which the PWM to PSM transition occurs.
Figure 4: PWM to PSM threshold for Analog Devices’ ADP2108.
Other power component manufacturers also offer dual-mode switching converters. Linear Technology supplies the LTC3412A
, which features both “Burst Mode” and pulse-skipping operation to improve efficiency at low loads. The chip is a buck converter that can operate across an input range of 2.25 to 5.5 V providing an output of 0.8 to 5 V at up to 3 A.
Burst Mode is an example of the intermediate PFM technique described above that improves efficiency while maintaining reasonable transient response. For example, by implementing Burst Mode, the efficiency at 10 mA output current (VIN
3.3 V, VOUT
2.5 V) is improved from 30 to 90 percent. The LTC3412A also includes a conventional pulse-skipping operational mode that further reduces switching losses at low loads.
Extending battery life
PWM-controlled switching converters are the popular choice when a design engineer needs to extend battery life in a portable product. However, it’s important to remember that many portable products spend a lot of time in low-power sleep modes just at the point of operation where the converter is at its least efficient. Although the demand on the battery is modest, over the long term the current adds up and battery life is compromised.
By employing a converter that uses a PWM architecture but that benefits from PFM or other PSM techniques below a certain load threshold, the designer can benefit from the advantages of PWM during normal operation, but preserve battery capacity during the extended periods when many portable devices sit idle.