Sleeping Giants – Keeping Power Low in Larger Parts

By Jon Gabay

Contributed By Hearst Electronic Products


As more functionality is pushed into smaller yet more sophisticated devices, low power has become an unavoidably large concern. In particular, designs for handheld products with restrictive energy resources (such as battery power) and tight space constraints translates into having to squeeze more run time out of limited energy reserves.

Despite this, large processors are being directed to handle many independent I/O-based tasks while spending most of their time in low-power idle and sleep states. Since battery run time is a feature users are sensitive to, the engineer’s ability to manage energy in real time may dictate the success of the design. Nevertheless, physics is physics and we only have so many options. Fortunately, clever use of the options and resources we do have can still yield satisfactory results.

This article looks at several large processors that have low-energy features and target designs demanding energy efficiency. It examines techniques for reducing power draw, how peripherals can be managed dynamically and what types of energy and current draw numbers these parts are able to both claim and achieve. While microcontroller pin counts vary from 5 to 500, I chose all 100-pin parts in their respective families for more of an apples-to-apples comparison. Principles and techniques work for even larger pin counts so the information presented here can be extrapolated. All parts, datasheets, app notes, and development kits referenced here can be found on Digi-Key’s website.

Useful design techniques

Ohm’s law and circuit theory are very well understood, and there are only so many things we can do to lower energy consumption, especially as the circuits get smaller in size and larger in gate count. A major way to reduce power is to reduce voltage, and this is common practice. Through split power supplies (core, I/O, and peripheral specific power needs), on-chip regulators, or by employing a single homogenous low-voltage (mostly 1.6 to 1.8 V), microcontroller power requirements have been steadily dropping. This is something chipmakers do, and virtually everything we have at our disposal can run at lower voltages if we chose to do so.

Another key way to reduce power is to reduce the switching frequencies that drive our core processor logic, state machines, sequencers, and peripherals. Power consumption in digital circuits is directly proportional to the frequency at which they switch or clock (Figure 1), so a reduced clock frequency will reduce power in a corresponding way.

The power draw is directly proportional to switching frequency at the gate level

Figure 1: Especially with CMOS circuits, the power draw is directly proportional to switching frequency at the gate level. Getting the same performance at lower frequencies drastically reduces power.

While this technique will reduce processing performance directly, not everything has to have lower clock frequency. A core processor may be running at a high speed, but there is no reason that a UART needs to divide down an 11.0592 MHz clock to get a reliable 9,600-baud connection. If the chipmakers are smart, they will leave engineers options as to how to use our available clocks to drive our peripherals. Some do just that so you can run a low-energy UART from a 32.768 kHz frequency (1 clock versus 3,375 every second). This is true for A/D and D/A converters as well so sensor-based designs can also benefit from this technique.

Raw processor performance matters here as well. If a cranking processor can do all associated tasks in 1 ms before it has to go back to sleep, it is better off than a slower processor that must run for 20 ms. Sleep and low-power modes are often very effective, therefore getting into sleep mode faster can save significant energy. Similarly, wakeup times matter as well. Energy draw is higher when waking up so a fast wakeup means less overall higher power on time. Peripheral wakeup times also are important here, both on- and off-chip.

Another energy-lowering technique is the use of autonomous peripherals, either on- or off-chip, that can operate in a low-power background mode, without the need for any intervention from the host processor. A video or display processor can refresh the display without the need for processor intervention. It can also monitor the touchscreen and discern between real intent versus an erroneous contact. It should operate using less power than a core processor as well since often it is a refined, factored, reduced-state machine while running, requiring the least amount of active hardware.

Data converters are another part that can benefit from this technique (Figure 2). A sensor that needs to be monitored every millisecond can sleep while a timer kicks off conversion, transfers conversion results to memory, updates pointers and counters, and only wakes up the processor when a certain number of samples are ready for processing. The addition of a compare (either as an analog comparator, or a digital value threshold monitor), can be used to keep a processor asleep indefinitely until an “alarm” or “alert” level occurs. This saves all the wakeup, sniff, and go back to sleep energy.

An autonomous-state machine

Figure 2: An autonomous-state machine that can oversee a sequential process can keep the core in deep sleep for extended periods, saving a significant amount of power usage.

A key parameter to scrutinize in our example micros is the actual standby currents they claim to achieve. While these are good ballpark figures to help narrow the field, take these numbers as you would a grain of salt, since many other factors contribute to the overall power draw.

For example, what is the state of our I/O while the micro sleeps? These power consumption numbers are NOT included in any low-power numbers used by our suppliers since they depend on how we configure our I/O. If we are driving two 20 mA high-current I/O lines, and our sleep current is 100 µA, we are still burning 40.1 mA while in static and sleep state.

A few good candidates

Several MCU manufacturers tout low energy and reduced power capabilities, and it is our responsibility to know what we can believe and what we cannot. The way in which these numbers are determined matters more than the numbers at hand. Despite this, the published specs and capabilities are a good place to start when looking for processors that meet our performance needs and can operate in low-power modes.

Take for instance Atmel’s SAM4Lx family of ARM® Cortex™-M4 processors featuring its proprietary picoPower technology. This 48 MHz part has active current consumption as low as 90 µA/MHz. It touts its fast 1.5 µs wakeup time, which is an important figure. In addition, its low-power modes with RAM retention go down to 3 and 1.5 µA, respectively, for its wait and retention modes.

Take note of Atmel’s low-power 32.768 kHz clock for RTC and devices. A slow R/C clock can also be switched-in to lower power draw even more. The internal PLL can be kicked-in up to 240 MHz for burst of USB high-speed data, and then shut down again to save power. The 100-pin ATSAM4LC2CA-AU has 80 I/Os, which include six high-drive-current sink-source pins from as low as 1.68 V input voltage. This part draws only 218 µA/MHz (up to 48 MHz), while drawing 6.9 µA in low-power mode.

An interesting block inside the SAM4L is the power-management block that generates clock and resets, and performs on-the-fly frequency changing of the CPU, high-speed buses, and peripheral bus clocks (Figure 3). Mask registers hold divider levels for clocks, allowing all to run at different speeds to save power. In addition, shutdowns of peripherals or functional blocks do not need to occur when on-the-fly frequency changing occurs and unused peripherals can turn off the clock completely.

On-the-fly clock changing for CPU, buses, and peripherals

Figure 3: On-the-fly clock changing for CPU, buses, and peripherals are controlled through a dedicated power-management unit that can also turn off clocks completely to peripherals that are not used.

Several other power-optimizing peripherals and features are embedded here as well, including a glue logic controller, a parallel capture mode, analog comparators with window detection, and an independent peripheral event detection system that allows direct peripheral-to-peripheral communications keeping the core asleep.

On a comparable scale, let us also look at the STM32-L1 series from STMicroelectronics. This part boasts low power consumption thanks to an ultra-low-leakage process technology. In particular, we will examine the STM32L151VBT6, which is the 100-pin version with 83 I/Os. Also operating down to 1.65 V, this part can run from 32 kHz up to 32 MHz at 214 µA/MHz. While its wakeup time of <8 µs is not as fast as some, it does feature a low-power 9 µA run mode.

Some nice features here include the two ultra-low-power comparators and the low-power 12-bit A/D and D/A converters with up to 1 Msample/s rates (when VCC is 2.4 V or higher). A nice “ZEROPOWER” power-on reset can be tightly coupled with the brownout reset circuitry, and the many sleep, snooze, and low-power modes provide some flexibility to keep certain peripherals alive while the core and other peripherals sleep. This part also has 32.768 kHz clocks and a fairly flexible distribution scheme for clocking.

An interesting low-power offering from Texas Instruments is worth looking at as well. The well-known MSP430 family has several parts optimized to lower-energy use such as the 100-pin MSP430F5436IPZR. While only operating from 2.2 V minimum, it is a 16-bit internal architecture (which intrinsically can save energy by not having to keep such wide registers powered) and draws just 1.8 µA in standby mode with RAM retention.

Also featured in its low-power arsenal are a 5 µs wakeup time and 226 µA/MHz current draw. The part further offers a low-power oscillator and can run up to 18 MHz. The MSP430 family includes members that combine various peripherals targeting specific applications. Different flavors include 12-bit A/D converters, internal references, sample and holds, and auto-scan features.

One active mode is provided, but five software-selectable low-power modes are available, keeping different functions and peripherals alive. Drive strength on all I/O ports is programmable and up to ten 8-bit I/O ports can be defined for easier parallel interfacing.

An Ultra-Low-Power MSP430 Training Module is available from TI on Digi-Key’s website for the MSP430, as are several other Product Training Modules describing peripherals, design tools, clocking systems, and more.

An interesting and effective low-power processor solution comes from Silicon Labs with its 48 MHz Giant Gecko ARM 32-bit Cortex-M3, 100-pin (86 I/O) processor – the EFM32GG280F1024-QFP100. This part, and others from the family of Gecko parts, were designed from the ground up to have low-energy peripherals (low-energy UART, A/D. D/A, and more), fast wakeups (2 µs), autonomous peripherals and embedded hardware to facilitate low-energy modes that can extend battery run times.

At full-power mode with everything turned on and running, the part offers a very-low 150 µA/MHz power consumption. Four other low-power and sleep modes keep select peripherals and RAM alive. In addition, like several other processors in this class, the Geckos use a flexible clocking scheme with both high- and low-frequency crystal and R/C oscillators to allow different stages to be clock and power optimized.

The Gecko MCUs take autonomous functionality to a higher level using what the company calls a reflex bus inside the part. This is an interconnecting state-machine-based mechanism that is akin to passing a baton from one peripheral to another, all while the micro sleeps. The supplier’s LESENSE feature makes it possible to design ultra-low-power sensor interfaces with autonomous conditional monitoring. Without using the microcontroller CPU, the EFM32 family can monitor and react to 16 sensors while keeping energy consumption to a minimum. The LESENSE low-power sensor interface also supports the on-chip analog comparators, op amps, and a very handy event detector. This allows complex chains of events to take place in a low-power background state without ever having to wake up the core processor (Figure 4).

Quadrature metal sensor using Hall-Effect devices

Figure 4: Combining several low-energy features, this example illustrates a quadrature metal sensor using Hall-Effect devices that do not wake up the processor until some fairly high-level decision-making has taken place. The oscillator will vary in frequency and amplitude depending on the presence of metal. Once biased, clever use of the event detector will tell engineers that the desired event we are looking for has occurred. Then we wake up our processor.

Another application example cited by Silicon Labs is a self-oscillating capacitive touchscreen sensor that only wakes up the host processor when a valid touch occurs. In a similar manner, sensors can be monitored while the core sleeps and only wakes up for alarm conditions.

Less can be more

The best approach to lower-energy designs, especially with a lot of I/O, is a combination of hardware features, resources, and a clever approach to coding your design. Rather than a FOR or a WHILE loop, putting the micro to sleep and waking it up from a timer or event saves power.

Similarly, being able to program drive strengths on every I/O, and even disabling internal pull-ups so you can use higher-value external ones, can contribute to squeezing every microjoule of energy out of your energy source. It is nice to know that these parts are ready to help, offering a wide selection of low-energy features.

For more information on the parts discussed in this article, use the links provided to access product information pages on the Digi-Key website.

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